45 #define MAX_PA_VALUE 14 46 #define MIN_PA_VALUE -31 48 #define VCO_CENTER_FREQ 3600000000 50 #define HIGH_BAND_FACTOR 4 51 #define MIDDLE_BAND_FACTOR 8 53 #define HIGH_BAND_LOWER_LIMIT 825900000 54 #define HIGH_BAND_UPPER_LIMIT 1056000000 55 #define MIDDLE_BAND_LOWER_LIMIT 412900000 56 #define MIDDLE_BAND_UPPER_LIMIT 527100000 58 #define MINIMUM_DATARATE 100 59 #define MAXIMUM_DATARATE 250000 71 #define IS_PA_MAX_INDEX(INDEX) ((INDEX)<=7) 72 #define IS_PAPOWER_DBM(PATABLE) ((PATABLE)>= (MIN_PA_VALUE) && (PATABLE)<=(MAX_PA_VALUE)) 73 #define IS_PAPOWER(PATABLE) ((PATABLE)<=90) 74 #define IS_PA_STEP_WIDTH(WIDTH) ((WIDTH)>=1 && (WIDTH)<=4) 76 #define IS_MODULATION(MOD) (((MOD) == MOD_NO_MOD) || \ 77 ((MOD) == MOD_2FSK) || \ 78 ((MOD) == MOD_4FSK) || \ 79 ((MOD) == MOD_2GFSK_BT05) || \ 80 ((MOD) == MOD_2GFSK_BT1) || \ 81 ((MOD) == MOD_4GFSK_BT05) || \ 82 ((MOD) == MOD_4GFSK_BT1) || \ 83 ((MOD) == MOD_ASK_OOK) || \ 86 #define IS_AFC_MODE(MODE) (MODE<=1) 87 #define IS_AFC_GAIN(GAIN) (GAIN<=15) 88 #define IS_ISI_EQU(MODE) (MODE<=2) 89 #define IS_CLKREC_MODE(MODE) (MODE<=1) 90 #define IS_CLKREC_P_GAIN(GAIN) (GAIN<=7) 91 #define IS_CLKREC_I_GAIN(GAIN) (GAIN<=15) 94 #define IS_FREQUENCY_BAND_HIGH(FREQUENCY) ((FREQUENCY)>=HIGH_BAND_LOWER_LIMIT && \ 95 (FREQUENCY)<=HIGH_BAND_UPPER_LIMIT) 97 #define IS_FREQUENCY_BAND_MIDDLE(FREQUENCY) ((FREQUENCY)>=MIDDLE_BAND_LOWER_LIMIT && \ 98 (FREQUENCY)<=MIDDLE_BAND_UPPER_LIMIT) 100 #define IS_FREQUENCY_BAND(FREQUENCY) (IS_FREQUENCY_BAND_HIGH(FREQUENCY) || \ 101 IS_FREQUENCY_BAND_MIDDLE(FREQUENCY)) 103 #define IS_CHANNEL_SPACE(CHANNELSPACE, F_Xo) (CHANNELSPACE<=(F_Xo/32768*255)) 106 #define IS_DATARATE(DATARATE, F_CLK) (DATARATE>=MINIMUM_DATARATE && DATARATE<=((uint64_t)MAXIMUM_DATARATE*F_CLK/1000000)/26) 109 #define F_DEV_LOWER_LIMIT(F_Xo) (F_Xo>>22) 110 #define F_DEV_UPPER_LIMIT(F_Xo) (((uint64_t)787109*F_Xo/1000000)/26) 111 #define IS_F_DEV(FDEV,F_Xo) (FDEV>=F_DEV_LOWER_LIMIT(F_Xo) && FDEV<=F_DEV_UPPER_LIMIT(F_Xo)) 113 #define CH_BW_LOWER_LIMIT(F_CLK) (((uint64_t)1100*F_CLK/1000000)/26) 114 #define CH_BW_UPPER_LIMIT(F_CLK) (((uint64_t)800100*F_CLK/1000000)/26) 116 #define IS_CH_BW(BW,F_Xo) ((BW)>=CH_BW_LOWER_LIMIT(F_Xo) && (BW)<=CH_BW_UPPER_LIMIT(F_Xo)) 130 static uint32_t s_lXtalFrequency=50000000;
138 static const uint16_t s_vectnBandwidth26M[90]=
140 8001, 7951, 7684, 7368, 7051, 6709, 6423, 5867, 5414, \
141 4509, 4259, 4032, 3808, 3621, 3417, 3254, 2945, 2703, \
142 2247, 2124, 2015, 1900, 1807, 1706, 1624, 1471, 1350, \
143 1123, 1062, 1005, 950, 903, 853, 812, 735, 675, \
144 561, 530, 502, 474, 451, 426, 406, 367, 337, \
145 280, 265, 251, 237, 226, 213, 203, 184, 169, \
146 140, 133, 126, 119, 113, 106, 101, 92, 84, \
147 70, 66, 63, 59, 56, 53, 51, 46, 42, \
148 35, 33, 31, 30, 28, 27, 25, 23, 21, \
149 18, 17, 16, 15, 14, 13, 13, 12, 11
172 void S2LPRadioSearchWCP(uint8_t* cp_isel, uint8_t* pfd_split, uint32_t lFc, uint8_t refdiv);
194 uint32_t lDatarateTmp, f_dig=s_lXtalFrequency;
196 uint64_t tgt1,tgt2,tgt;
203 for(uDrE = 0; uDrE != 12; uDrE++) {
205 if(lDatarate<=lDatarateTmp)
208 (*pcE) = (uint8_t)uDrE;
211 tgt=((uint64_t)lDatarate)<<32;
212 (*pcM) = (uint16_t)(tgt/f_dig);
213 tgt1=(uint64_t)f_dig*(*pcM);
214 tgt2=(uint64_t)f_dig*((*pcM)+1);
217 tgt=((uint64_t)lDatarate)<<(33-uDrE);
218 (*pcM) = (uint16_t)((tgt/f_dig)-65536);
219 tgt1=(uint64_t)f_dig*((*pcM)+65536);
220 tgt2=(uint64_t)f_dig*((*pcM)+1+65536);
224 (*pcM)=((tgt2-tgt)<(tgt-tgt1))?((*pcM)+1):(*pcM);
240 uint64_t tgt1,tgt2,tgt;
242 s_assert_param(IS_F_DEV(lFDev, s_lXtalFrequency));
245 if((tmp&BS_REGMASK) == 0) {
254 for(uFDevE = 0; uFDevE != 12; uFDevE++) {
259 (*pcE) = (uint8_t)uFDevE;
263 tgt=((uint64_t)lFDev)<<22;
264 (*pcM)=(uint32_t)(tgt/s_lXtalFrequency);
265 tgt1=(uint64_t)s_lXtalFrequency*(*pcM);
266 tgt2=(uint64_t)s_lXtalFrequency*((*pcM)+1);
270 tgt=((uint64_t)lFDev)<<(23-uFDevE);
271 (*pcM)=(uint32_t)(tgt/s_lXtalFrequency)-256;
272 tgt1=(uint64_t)s_lXtalFrequency*((*pcM)+256);
273 tgt2=(uint64_t)s_lXtalFrequency*((*pcM)+1+256);
276 (*pcM)=((tgt2-tgt)<(tgt-tgt1))?((*pcM)+1):(*pcM);
294 uint32_t f_dig=s_lXtalFrequency;
295 int32_t chfltCalculation[3];
302 s_assert_param(IS_CH_BW(lBandwidth,f_dig));
305 for(i=0;i<90 && (lBandwidth<(uint32_t)(((uint64_t)s_vectnBandwidth26M[i]*f_dig)/260000));i++);
311 for(uint8_t j=0;j<3;j++) {
312 if(((i_tmp+j-1)>=0) && ((i_tmp+j-1)<=89)) {
313 chfltCalculation[j] = (int32_t)lBandwidth - (int32_t)(((uint64_t)s_vectnBandwidth26M[i_tmp+j-1]*f_dig)/260000);
316 chfltCalculation[j] = 0x7FFFFFFF;
319 uint32_t chfltDelta = 0xFFFFFFFF;
321 for(uint8_t j=0;j<3;j++) {
322 if(S_ABS(chfltCalculation[j])<chfltDelta) {
323 chfltDelta = S_ABS(chfltCalculation[j]);
328 (*pcE) = (uint8_t)(i/9);
329 (*pcM) = (uint8_t)(i%9);
343 uint32_t f_dig=s_lXtalFrequency;
351 dr=((uint64_t)f_dig*cM);
352 return (uint32_t)(dr>>32);
355 dr=((uint64_t)f_dig)*((uint64_t)cM+65536);
357 return (uint32_t)(dr>>(33-cE));
370 uint32_t f_xo=s_lXtalFrequency;
373 return (uint32_t)(((uint64_t)f_xo*cM)>>22);
376 return (uint32_t)(((uint64_t)f_xo*(256+cM))>>(23-cE));
388 uint32_t f_dig=s_lXtalFrequency;
394 return (uint32_t)((uint64_t)100*s_vectnBandwidth26M[cM+(cE*9)]*f_dig/26000000);
408 return (uint32_t)((((uint64_t)s_lXtalFrequency*lSynthWord)>>19)/bs/refdiv);
422 if(IS_FREQUENCY_BAND_HIGH(frequency)) {
429 uint64_t tgt1,tgt2,tgt;
432 tgt = (((uint64_t)frequency)<<19)*(band*refdiv);
433 synth=(uint32_t)(tgt/s_lXtalFrequency);
434 tgt1 = (uint64_t)s_lXtalFrequency*(synth);
435 tgt2 = (uint64_t)s_lXtalFrequency*(synth+1);
437 synth=((tgt2-tgt)<(tgt-tgt1))?(synth+1):(synth);
451 return (uint32_t)(((uint64_t)lChannelSpace)<<15)/s_lXtalFrequency;
463 return (uint32_t)(((uint64_t)s_lXtalFrequency*cChSpaceRegVal)>>15);
477 uint32_t f_dig=s_lXtalFrequency;
483 (*pcAnaIf)=(uint8_t)((((uint64_t)nIF)<<13)*3/s_lXtalFrequency-100);
484 (*pcDigIf)=(uint8_t)((((uint64_t)nIF)<<13)*3/f_dig-100);
501 uint32_t vcofreq, lFRef;
504 s_assert_param(IS_FREQUENCY_BAND(lFc));
507 if(IS_FREQUENCY_BAND_HIGH(lFc)) {
512 vcofreq = lFc*BFactor;
515 lFRef = s_lXtalFrequency/refdiv;
561 uint8_t tmpBuffer[6], tmp8, dr_e, fdev_m, fdev_e, bw_m, bw_e;
565 s_assert_param(IS_FREQUENCY_BAND(pxSRadioInitStruct->
lFrequencyBase));
567 s_assert_param(IS_DATARATE(pxSRadioInitStruct->
lDatarate,s_lXtalFrequency));
568 s_assert_param(IS_F_DEV(pxSRadioInitStruct->
lFreqDev,s_lXtalFrequency));
577 for(
volatile uint8_t i=0; i!=0xFF; i++);
586 for(
volatile uint8_t i=0; i!=0xFF; i++);
591 if(xState==S_ENABLE) {
592 s_assert_param(IS_CH_BW(pxSRadioInitStruct->
lBandwidth,(s_lXtalFrequency>>1)));
595 s_assert_param(IS_CH_BW(pxSRadioInitStruct->
lBandwidth,s_lXtalFrequency));
604 tmpBuffer[0] = (uint8_t)(dr_m>>8);
605 tmpBuffer[1] = (uint8_t)dr_m;
612 S2LPSpiReadRegisters(
MOD1_ADDR, 1, &tmpBuffer[3]);
613 tmpBuffer[3] &= ~FDEV_E_REGMASK;
614 tmpBuffer[3] |= fdev_e;
615 tmpBuffer[4] = fdev_m;
619 tmpBuffer[5] = (bw_m<<4) | bw_e;
622 S2LPSpiWriteRegisters(
MOD4_ADDR, 6, tmpBuffer);
629 tmpBuffer[0] &= 0x7F;
630 tmpBuffer[1] &= 0xFD;
634 tmpBuffer[0] |= 0x80;
635 tmpBuffer[1] |= 0x02;
646 else if(pxSRadioInitStruct->
lDatarate<32000)
650 else if(pxSRadioInitStruct->
lDatarate<62500)
661 S2LPSpiReadRegisters(
AFC2_ADDR, 1, &tmp8);
662 tmp8 |= AFC_FREEZE_ON_SYNC_REGMASK; S2LPSpiWriteRegisters(
AFC2_ADDR, 1, &tmp8);
677 uint8_t tmpBuffer[6];
678 uint8_t band, cRefDiv, dr_e, fdev_m, fdev_e, bw_e, bw_m;
682 S2LPSpiReadRegisters(
SYNT3_ADDR, 4, tmpBuffer);
685 if(tmpBuffer[0] & BS_REGMASK) {
693 tmp32 = (((uint32_t)(tmpBuffer[0] & SYNT_27_24_REGMASK))<<24) | (((uint32_t)tmpBuffer[1])<<16) | (((uint32_t)tmpBuffer[2])<<8) | ((uint32_t)tmpBuffer[3]);
707 fdev_m = tmpBuffer[4];
708 fdev_e = tmpBuffer[3] & FDEV_E_REGMASK;
711 bw_m = (tmpBuffer[5] & CHFLT_M_REGMASK)>>4;
712 bw_e = tmpBuffer[5] & CHFLT_E_REGMASK;
715 dr_m = ((uint16_t)tmpBuffer[0]<<8) | ((uint16_t)tmpBuffer[1]);
716 dr_e = tmpBuffer[2] & DATARATE_E_REGMASK;
737 uint8_t tmpBuffer[4];
741 tmp &= ~SYNT_27_24_REGMASK;
744 tmpBuffer[0] = (((uint8_t)(lSynthWord>>24)) & SYNT_27_24_REGMASK) | tmp;
745 tmpBuffer[1] = (uint8_t)(lSynthWord>>16);
746 tmpBuffer[2] = (uint8_t)(lSynthWord>>8);
747 tmpBuffer[3] = (uint8_t)lSynthWord;
760 uint8_t tmpBuffer[4];
762 return ((((uint32_t)(tmpBuffer[0] & SYNT_27_24_REGMASK))<<24) | (((uint32_t)tmpBuffer[1])<<16) | (((uint32_t)tmpBuffer[2])<<8) | ((uint32_t)tmpBuffer[3]));
799 s_assert_param(IS_SFUNCTIONAL_STATE(xNewState));
803 if(xNewState == S_ENABLE) {
804 tmp |= REFDIV_REGMASK;
806 tmp &= ~REFDIV_REGMASK;
823 if(tmp & REFDIV_REGMASK) {
840 s_assert_param(IS_SFUNCTIONAL_STATE(xNewState));
844 if(xNewState == S_ENABLE) {
845 tmp &= ~PD_CLKDIV_REGMASK;
847 tmp |= PD_CLKDIV_REGMASK;
863 if(tmp & PD_CLKDIV_REGMASK) {
909 uint8_t tmpBuffer[4], cp_isel, bs = 1, pfd_split, tmp, cRefDiv;
911 s_assert_param(IS_FREQUENCY_BAND(lFBase));
915 if(IS_FREQUENCY_BAND_HIGH(lFBase)) {
925 tmp &= ~PLL_PFD_SPLIT_EN_REGMASK;
926 tmp |= (pfd_split<<2);
930 tmpBuffer[0] = (((uint8_t)(tmp32>>24)) & SYNT_27_24_REGMASK) | cp_isel<<5 | (bs<<4) ;
931 tmpBuffer[1] = (uint8_t)(tmp32>>16);
932 tmpBuffer[2] = (uint8_t)(tmp32>>8);
933 tmpBuffer[3] = (uint8_t)tmp32;
948 uint8_t tmpBuffer[4];
950 uint8_t cRefDiv, band;
956 if(tmpBuffer[0] & BS_REGMASK) {
965 tmp32 = (((uint32_t)(tmpBuffer[0] & SYNT_27_24_REGMASK))<<24) | (((uint32_t)tmpBuffer[1])<<16) | (((uint32_t)tmpBuffer[2])<<8) | ((uint32_t)tmpBuffer[3]);
980 uint8_t dr_e, tmpBuffer[3];
984 s_assert_param(IS_DATARATE(lDatarate,s_lXtalFrequency/2));
987 s_assert_param(IS_DATARATE(lDatarate,s_lXtalFrequency));
994 S2LPSpiReadRegisters(
MOD4_ADDR, 3, tmpBuffer);
997 tmpBuffer[0] = (uint8_t)(dr_m>>8);
998 tmpBuffer[1] = (uint8_t)dr_m;
999 tmpBuffer[2] &= ~DATARATE_E_REGMASK;
1000 tmpBuffer[2] |= dr_e;
1015 uint8_t tmpBuffer[3], dr_e;
1019 dr_m = (((uint16_t)tmpBuffer[0])<<8) | ((uint16_t)tmpBuffer[1]);
1020 dr_e = tmpBuffer[2]&DATARATE_E_REGMASK;
1034 uint8_t uFDevM, uFDevE, tmpBuffer[2];
1036 s_assert_param(IS_F_DEV(lFDev, s_lXtalFrequency));
1041 S2LPSpiReadRegisters(
MOD1_ADDR, 2, tmpBuffer);
1042 tmpBuffer[0] &= ~FDEV_E_REGMASK;
1043 tmpBuffer[0] |= uFDevE;
1044 tmpBuffer[1] = uFDevM;
1061 if((tmp&BS_REGMASK) == 0) {
1066 S2LPSpiReadRegisters(
MOD1_ADDR, 2, tmpBuffer);
1067 uFDevE = tmpBuffer[0] & FDEV_E_REGMASK;
1085 uint8_t uBwM, uBwE, tmpBuffer;
1089 s_assert_param(IS_CH_BW(lBandwidth,(s_lXtalFrequency>>1)));
1092 s_assert_param(IS_CH_BW(lBandwidth,(s_lXtalFrequency)));
1097 tmpBuffer = (uBwM<<4)|(uBwE);
1111 uint8_t tmpBuffer, uBwM, uBwE;
1115 uBwM = (tmpBuffer&0xF0)>>4;
1116 uBwE = tmpBuffer&0x0F;
1132 s_assert_param(IS_MODULATION(xModulation));
1134 S2LPSpiReadRegisters(
MOD2_ADDR, 1, &tmpBuffer);
1135 tmpBuffer &= ~MOD_TYPE_REGMASK;
1136 tmpBuffer |= xModulation;
1164 s_lXtalFrequency = lXtalFrequency;
1175 return s_lXtalFrequency;
1190 if(xNewState == S_ENABLE) {
1191 tmp |= PA_MAXDBM_REGMASK;
1193 tmp &= ~PA_MAXDBM_REGMASK;
1211 uint8_t address, paLevelValue;
1212 s_assert_param(IS_PA_MAX_INDEX(cIndex));
1213 s_assert_param(IS_PAPOWER_DBM(lPowerdBm));
1220 paLevelValue = (uint8_t)((int32_t)29-2*lPowerdBm);
1225 g_xStatus = S2LPSpiWriteRegisters(address, 1, &paLevelValue);
1240 uint8_t address, paLevelValue;
1241 s_assert_param(IS_PA_MAX_INDEX(cIndex));
1245 g_xStatus = S2LPSpiReadRegisters(address, 1, &paLevelValue);
1247 return ((int32_t)29-paLevelValue)/2;
1259 s_assert_param(IS_PA_MAX_INDEX(cIndex));
1262 tmp &= (~PA_LEVEL_MAX_IDX_REGMASK);
1277 return (tmp & PA_LEVEL_MAX_IDX_REGMASK);
1294 uint8_t tmpBuffer[2];
1298 if(xNewState == S_ENABLE) {
1299 tmpBuffer[0] &= ~PA_MAXDBM_REGMASK;
1300 tmpBuffer[0] &= ~PA_RAMP_EN_REGMASK;
1301 tmpBuffer[1] |= FIR_EN_REGMASK;
1303 tmpBuffer[1] &= ~FIR_EN_REGMASK;
1322 uint8_t tmpBuffer[2];
1326 if(xNewState == S_ENABLE) {
1327 tmpBuffer[0] &= ~PA_MAXDBM_REGMASK;
1328 tmpBuffer[0] |= PA_RAMP_EN_REGMASK;
1329 tmpBuffer[1] &= ~FIR_EN_REGMASK;
1331 tmpBuffer[0] &= ~PA_RAMP_EN_REGMASK;
1347 s_assert_param(IS_SFUNCTIONAL_STATE(xAmplitudeCalibration));
1348 s_assert_param(IS_SFUNCTIONAL_STATE(xFrequencyCalibration));
1352 if(xAmplitudeCalibration == S_ENABLE) {
1353 tmp |= VCO_CALAMP_EXT_SEL_REGMASK;
1355 tmp &= ~VCO_CALAMP_EXT_SEL_REGMASK;
1358 if(xFrequencyCalibration == S_ENABLE) {
1359 tmp |= VCO_CALFREQ_EXT_SEL_REGMASK;
1361 tmp &= ~VCO_CALFREQ_EXT_SEL_REGMASK;
1384 value &= VCO_CALAMP_RX_REGMASK;
1416 uint8_t tmpBuffer[3];
1417 s_assert_param(IS_SFUNCTIONAL_STATE(xSAfcInit->
xAfcEnable));
1419 s_assert_param(IS_AFC_MODE(xSAfcInit->
xAfcMode));
1424 S2LPSpiReadRegisters(
AFC2_ADDR, 1, &tmpBuffer[0]);
1428 tmpBuffer[0] |= AFC_ENABLED_REGMASK;
1431 tmpBuffer[0] &= ~AFC_ENABLED_REGMASK;
1436 tmpBuffer[0] |= AFC_FREEZE_ON_SYNC_REGMASK;
1439 tmpBuffer[0] &= ~AFC_FREEZE_ON_SYNC_REGMASK;
1443 if(xSAfcInit->
xAfcMode == AFC_MODE_LOOP_CLOSED_ON_SLICER) {
1444 tmpBuffer[0] &= ~AFC_MODE_REGMASK;
1447 tmpBuffer[0] |= AFC_MODE_REGMASK;
1464 uint8_t tmpBuffer[3];
1466 S2LPSpiReadRegisters(
AFC2_ADDR, 3, tmpBuffer);
1473 xSAfcInit->
cAfcFastGain = (tmpBuffer[2] & AFC_FAST_GAIN_REGMASK)>>4;
1474 xSAfcInit->
cAfcSlowGain = (tmpBuffer[2] & AFC_SLOW_GAIN_REGMASK);
1487 s_assert_param(IS_ISI_EQU(xSIsiMode));
1490 tmp &= ~EQU_CTRL_REGMASK;
1491 tmp |= (((uint8_t)xSIsiMode)<<5);
1506 return (
SIsiEqu)((tmp&EQU_CTRL_REGMASK)>>5);
1518 uint8_t tmpBuffer[2] = {0x00, 0x00};
1519 s_assert_param(IS_CLKREC_MODE(xSSymClkRecInit->
xSClkRecMode));
1528 tmpBuffer[0] |= CLK_REC_ALGO_SEL_REGMASK;
1535 tmpBuffer[1] |= PSTFLT_LEN_REGMASK;
1551 uint8_t tmpBuffer[2];
1556 xSSymClkRecInit->
cClkRecIGainSlow = tmpBuffer[0]&CLK_REC_I_GAIN_SLOW_REGMASK;
1557 xSSymClkRecInit->
cClkRecPGainSlow = (tmpBuffer[0]&CLK_REC_P_GAIN_SLOW_REGMASK)>>5;
1560 xSSymClkRecInit->
cClkRecIGainFast = tmpBuffer[0]&CLK_REC_I_GAIN_FAST_REGMASK;
1561 xSSymClkRecInit->
cClkRecPGainFast = (tmpBuffer[0]&CLK_REC_P_GAIN_FAST_REGMASK)>>5;
uint32_t S2LPRadioComputeFrequencyBase(uint32_t lSynthWord, uint8_t bs, uint8_t refdiv)
Computes a frequency from a given SYNTH word.
uint32_t S2LPRadioGetXtalFrequency(void)
Return the XTAL frequency.
uint32_t S2LPRadioGetChannelSpace(void)
Return the channel space register.
uint8_t S2LPRadioSetFrequencyBase(uint32_t lFBase)
Set the Synth word and the Band Select register according to desired base carrier frequency....
#define CH_SPACE_ADDR
CH_SPACE register.
ModulationSelect xModulationSelect
void S2LPRadioSetMaxPALevel(SFunctionalState xNewState)
Set the MAX_DBM bit. This will allow to transmit at the maximum power.
void S2LPRadioSearchFreqDevME(uint32_t lFDev, uint8_t *pcM, uint8_t *pcE)
Returns the mantissa and exponent, whose value used in the frequency deviation formula will give a fr...
#define AFC2_ADDR
AFC2 register.
void S2LPRadioSetRefDiv(SFunctionalState xNewState)
Set the reference divider value.
void S2LPRadioSetPALeveldBm(uint8_t cIndex, int32_t lPowerdBm)
Sets a specific PA_LEVEL register, with a value given in dBm.
#define MOD1_ADDR
MOD1 register.
SFunctionalState
S2LP Functional state. Used to enable or disable a specific option.
void S2LPRadioSetSynthWord(uint32_t lSynthWord)
Sets the SYNTH registers.
void S2LPRadioSetPALevelMaxIndex(uint8_t cIndex)
Sets a specific PA_LEVEL_MAX_INDEX.
void S2LPRadioSearchDatarateME(uint32_t lDatarate, uint16_t *pcM, uint8_t *pcE)
Returns the mantissa and exponent, whose value used in the datarate formula will give the datarate va...
#define CHNUM_ADDR
CHNUM register.
SIsiEqu S2LPRadioGetIsiEqualizationMode(void)
Returnthe ISI equalization.
#define SYNTH_CONFIG2_ADDR
SYNTH_CONFIG2 register.
void S2LPRadioSetAutoRampingMode(SFunctionalState xNewState)
Set the autoramping mode. If enabled:
void S2LPRadioSetDigDiv(SFunctionalState xNewState)
Set the digital divider .
SFunctionalState xAfcEnable
uint32_t S2LPRadioComputeSynthWord(uint32_t frequency, uint8_t refdiv)
Computes the synth word from a given frequency.
#define VCO_CONFIG_ADDR
VCO_CONFIG register.
SIsiEqu
S2LP ISI Equalization type enumeration.
void S2LPRadioSetFrequencyDev(uint32_t lFDev)
Set the frequency deviation.
#define PA_POWER8_ADDR
PA_POWER8 register.
S2LP Radio Init structure definition.
void S2LPRadioCalibrationVco(SFunctionalState xAmplitudeCalibration, SFunctionalState xFrequencyCalibration)
Enable the calibration of the VCO frequency and amplitude.
void S2LPRadioSetRxCalibVcoAmpWord(uint8_t value)
Set calibration word of the aplitude in RX.
#define DIG_DOMAIN_XTAL_THRESH
uint8_t S2LPRadioGetChannel(void)
Returns the actual channel number.
int32_t S2LPRadioGetPALeveldBm(uint8_t cIndex)
Returns a specific PA_LEVEL register, returning a value in dBm.
uint32_t S2LPRadioComputeChannelSpacing(uint8_t cChSpaceRegVal)
Compute the channel spacing register from the channel spacing given in Hz. The channel spacing step i...
S2LP AFC Init structure definition.
void S2LPRadioSetModulation(ModulationSelect xModulation)
Set the modulation type.
uint8_t S2LPRadioComputeChannelSpacingRegValue(uint32_t lChannelSpace)
Computes the channel space register staring from the channel space value in Hz. The channel spacing s...
void S2LPRadioSetIsiEqualizationMode(SIsiEqu xSIsiMode)
Set the ISI equalizer.
#define MOD2_ADDR
MOD2 register.
ModulationSelect
S2LP Modulation enumeration.
void S2LPRadioSetChannel(uint8_t cChannel)
Sets the channel number.
SFunctionalState S2LPRadioGetDigDiv(void)
Get the digital divider .
SClkRecMode
S2LP Clock Recovery mode enumeration.
SFunctionalState cClkRec16SymPostFlt
uint8_t S2LPRadioInit(SRadioInit *pxSRadioInitStruct)
Initializes the S2LP analog and digital radio part according to the specified parameters in the pxSRa...
#define MIDDLE_BAND_FACTOR
void S2LPRadioSearchChannelBwME(uint32_t lBandwidth, uint8_t *pcM, uint8_t *pcE)
Returns the mantissa and exponent for a given bandwidth. Even if it is possible to pass as parameter ...
ModulationSelect S2LPRadioGetModulation(void)
Return the modulation type used.
uint32_t S2LPRadioGetSynthWord(void)
Returns the synth word.
void S2LPRefreshStatus(void)
Updates the gState (the global variable used to maintain memory of S2LP Status) reading the MC_STATE ...
uint32_t S2LPRadioGetFrequencyBase(void)
Return the base carrier frequency.
void S2LPRadioAfcInit(SAfcInit *xSAfcInit)
Initialize the AFC block according to the passed parameters.
uint32_t S2LPRadioComputeDatarate(uint16_t cM, uint8_t cE)
Returns the mantissa and exponent, whose value used in the datarate formula will give the datarate va...
void S2LPRadioSymClkRecoverInit(SSymClkRecInit *xSSymClkRecInit)
Clock recovery configuration.
void S2LPRadioSetChannelSpace(uint32_t lChannelSpace)
Set the channel space factor in channel space register. The channel spacing step is computed as F_Xo/...
uint32_t S2LPRadioComputeChannelFilterBw(uint8_t cM, uint8_t cE)
Computes the channel filter value starting from mantissa and exponent.
void S2LPRadioComputeIF(uint32_t nIF, uint8_t *pcAnaIf, uint8_t *pcPcDigIf)
Computes the ANALOG_IF and DIGITAL_IF register values staring from a image frequency value in Hz.
uint32_t S2LPRadioGetFrequencyDev(void)
Return the frequency deviation.
void S2LPRadioSetChannelBW(uint32_t lBandwidth)
Set the channel filter bandwidth.
uint32_t S2LPRadioGetDatarate(void)
Return the datarate.
S2LP Configuration and useful defines .
SAfcMode
S2LP AFC mode enumeration.
SFunctionalState S2LPRadioGetRefDiv(void)
To know if the reference deivider is enabled or disabled.
#define CHFLT_ADDR
CHFLT register.
void S2LPRadioGetSymClkRecoverInfo(SSymClkRecInit *xSSymClkRecInit)
Return the clock recovery configuration.
volatile S2LPStatus g_xStatus
S2LP Status global variable. This global variable of S2LPStatus type is updated on every SPI transact...
void S2LPRadioSetXtalFrequency(uint32_t lXtalFrequency)
Set the XTAL frequency.
void S2LPRadioGetInfo(SRadioInit *pxSRadioInitStruct)
Returns the S2LP analog and digital radio structure according to the registers value.
uint32_t S2LPRadioComputeFreqDeviation(uint8_t cM, uint8_t cE, uint8_t bs, uint8_t refdiv)
Returns the mantissa and exponent, whose value used in the datarate formula will give the datarate va...
#define ANT_SELECT_CONF_ADDR
ANT_SELECT_CONF register.
void S2LPRadioSetRxCalibVcoFreqWord(uint8_t value)
Set calibration word of the frequency in RX.
#define VCO_CALIBR_IN0_ADDR
VCO_CALIBR_IN0 register.
#define VCO_CALIBR_IN2_ADDR
VCO_CALIBR_IN2 register.
uint8_t S2LPRadioGetPALevelMaxIndex(void)
Returns the actual PA_LEVEL_MAX_INDEX.
void S2LPRadioSearchWCP(uint8_t *cp_isel, uint8_t *pfd_split, uint32_t lFc, uint8_t refdiv)
Returns the charge pump word for a given VCO frequency.
void S2LPRadioGetAfcInfo(SAfcInit *xSAfcInit)
Return the AFC struct that corresponds to the AFC block parameters set on the chip.
#define PA_POWER0_ADDR
PA_POWER0 register.
void S2LPRadioSetTxCalibVcoAmpWord(uint8_t value)
Set calibration word of the aplitude in TX.
S2LP Clock Recovery Init structure definition.
#define XO_RCO_CONF1_ADDR
XO_RCO_CONF1 register.
#define SYNT3_ADDR
SYNT3 register.
#define XO_RCO_CONF0_ADDR
XO_RCO_CONF0 register.
#define MOD4_ADDR
MOD4 register.
Header file for low level S2LP SPI driver.
uint32_t S2LPRadioGetChannelBW(void)
Return the channel filter bandwidth.
void S2LPRadioSetDatarate(uint32_t lDatarate)
Set the datarate.
#define CLOCKREC1_ADDR
CLOCKREC1 register.
void S2LPRadioSetTxCalibVcoFreqWord(uint8_t value)
Set calibration word of the frequency in TX.
#define VCO_CALIBR_IN1_ADDR
VCO_CALIBR_IN1 register.
SFunctionalState xAfcFreezeOnSync
Configuration and management of S2-LP RF Analog and Digital part.
#define IF_OFFSET_ANA_ADDR
IF_OFFSET_ANA register.
void S2LPRadioSetManualRampingMode(SFunctionalState xNewState)
Set the manual ramping mode.