This file contains all the registers address and masks. More...

Macros
#define	GPIO0_CONF_ADDR ((uint8_t)0x00)
	GPIO0_CONF register. More...

#define	GPIO1_CONF_ADDR ((uint8_t)0x01)
	GPIO1_CONF register. More...

#define	GPIO2_CONF_ADDR ((uint8_t)0x02)
	GPIO2_CONF register. More...

#define	GPIO3_CONF_ADDR ((uint8_t)0x03)
	GPIO3_CONF register. More...

#define	MCU_CK_CONF_ADDR ((uint8_t)0x04)
	MCU_CK_CONF register. More...

#define	SYNT3_ADDR ((uint8_t)0x05)
	SYNT3 register. More...

#define	SYNT2_ADDR ((uint8_t)0x06)
	SYNT2 register. More...

#define	SYNT1_ADDR ((uint8_t)0x07)
	SYNT1 register. More...

#define	SYNT0_ADDR ((uint8_t)0x08)
	SYNT0 register. More...

#define	IF_OFFSET_ANA_ADDR ((uint8_t)0x09)
	IF_OFFSET_ANA register. More...

#define	IF_OFFSET_DIG_ADDR ((uint8_t)0x0A)
	IF_OFFSET_DIG register. More...

#define	CH_SPACE_ADDR ((uint8_t)0x0C)
	CH_SPACE register. More...

#define	CHNUM_ADDR ((uint8_t)0x0D)
	CHNUM register. More...

#define	MOD4_ADDR ((uint8_t)0x0E)
	MOD4 register. More...

#define	MOD3_ADDR ((uint8_t)0x0F)
	MOD3 register. More...

#define	MOD2_ADDR ((uint8_t)0x10)
	MOD2 register. More...

#define	MOD1_ADDR ((uint8_t)0x11)
	MOD1 register. More...

#define	MOD0_ADDR ((uint8_t)0x12)
	MOD0 register. More...

#define	CHFLT_ADDR ((uint8_t)0x13)
	CHFLT register. More...

#define	AFC2_ADDR ((uint8_t)0x14)
	AFC2 register. More...

#define	AFC1_ADDR ((uint8_t)0x15)
	AFC1 register. More...

#define	AFC0_ADDR ((uint8_t)0x16)
	AFC0 register. More...

#define	RSSI_FLT_ADDR ((uint8_t)0x17)
	RSSI_FLT register. More...

#define	RSSI_TH_ADDR ((uint8_t)0x18)
	RSSI_TH register. More...

#define	ANT_SELECT_CONF_ADDR ((uint8_t)0x1F)
	ANT_SELECT_CONF register. More...

#define	CLOCKREC1_ADDR ((uint8_t)0x20)
	CLOCKREC1 register. More...

#define	CLOCKREC0_ADDR ((uint8_t)0x21)
	CLOCKREC0 register. More...

#define	PCKTCTRL6_ADDR ((uint8_t)0x2B)
	PCKTCTRL6 register. More...

#define	PCKTCTRL5_ADDR ((uint8_t)0x2C)
	PCKTCTRL5 register. More...

#define	PCKTCTRL4_ADDR ((uint8_t)0x2D)
	PCKTCTRL4 register. More...

#define	PCKTCTRL3_ADDR ((uint8_t)0x2E)
	PCKTCTRL3 register. More...

#define	PCKTCTRL2_ADDR ((uint8_t)0x2F)
	PCKTCTRL2 register. More...

#define	PCKTCTRL1_ADDR ((uint8_t)0x30)
	PCKTCTRL1 register. More...

#define	PCKTLEN1_ADDR ((uint8_t)0x31)
	PCKTLEN1 register. More...

#define	PCKTLEN0_ADDR ((uint8_t)0x32)
	PCKTLEN0 register. More...

#define	SYNC3_ADDR ((uint8_t)0x33)
	SYNC3 register. More...

#define	SYNC2_ADDR ((uint8_t)0x34)
	SYNC2 register. More...

#define	SYNC1_ADDR ((uint8_t)0x35)
	SYNC1 register. More...

#define	SYNC0_ADDR ((uint8_t)0x36)
	SYNC0 register. More...

#define	QI_ADDR ((uint8_t)0x37)
	QI register. More...

#define	PCKT_PSTMBL_ADDR ((uint8_t)0x38)
	PCKT_PSTMBL register. More...

#define	PROTOCOL2_ADDR ((uint8_t)0x39)
	PROTOCOL2 register. More...

#define	PROTOCOL1_ADDR ((uint8_t)0x3A)
	PROTOCOL1 register. More...

#define	PROTOCOL0_ADDR ((uint8_t)0x3B)
	PROTOCOL0 register. More...

#define	FIFO_CONFIG3_ADDR ((uint8_t)0x3C)
	FIFO_CONFIG3 register. More...

#define	FIFO_CONFIG2_ADDR ((uint8_t)0x3D)
	FIFO_CONFIG2 register. More...

#define	FIFO_CONFIG1_ADDR ((uint8_t)0x3E)
	FIFO_CONFIG1 register. More...

#define	FIFO_CONFIG0_ADDR ((uint8_t)0x3F)
	FIFO_CONFIG0 register. More...

#define	PCKT_FLT_OPTIONS_ADDR ((uint8_t)0x40)
	PCKT_FLT_OPTIONS register. More...

#define	PCKT_FLT_GOALS4_ADDR ((uint8_t)0x41)
	PCKT_FLT_GOALS4 register. More...

#define	PCKT_FLT_GOALS3_ADDR ((uint8_t)0x42)
	PCKT_FLT_GOALS3 register. More...

#define	PCKT_FLT_GOALS2_ADDR ((uint8_t)0x43)
	PCKT_FLT_GOALS2 register. More...

#define	PCKT_FLT_GOALS1_ADDR ((uint8_t)0x44)
	PCKT_FLT_GOALS1 register. More...

#define	PCKT_FLT_GOALS0_ADDR ((uint8_t)0x45)
	PCKT_FLT_GOALS0 register. More...

#define	TIMERS5_ADDR ((uint8_t)0x46)
	TIMERS5 register. More...

#define	TIMERS4_ADDR ((uint8_t)0x47)
	TIMERS4 register. More...

#define	TIMERS3_ADDR ((uint8_t)0x48)
	TIMERS3 register. More...

#define	TIMERS2_ADDR ((uint8_t)0x49)
	TIMERS2 register. More...

#define	TIMERS1_ADDR ((uint8_t)0x4A)
	TIMERS1 register. More...

#define	TIMERS0_ADDR ((uint8_t)0x4B)
	TIMERS0 register. More...

#define	CSMA_CONF3_ADDR ((uint8_t)0x4C)
	CSMA_CONF3 register. More...

#define	CSMA_CONF2_ADDR ((uint8_t)0x4D)
	CSMA_CONF2 register. More...

#define	CSMA_CONF1_ADDR ((uint8_t)0x4E)
	CSMA_CONF1 register. More...

#define	CSMA_CONF0_ADDR ((uint8_t)0x4F)
	CSMA_CONF0 register. More...

#define	IRQ_MASK3_ADDR ((uint8_t)0x50)
	IRQ_MASK3 register. More...

#define	IRQ_MASK2_ADDR ((uint8_t)0x51)
	IRQ_MASK2 register. More...

#define	IRQ_MASK1_ADDR ((uint8_t)0x52)
	IRQ_MASK1 register. More...

#define	IRQ_MASK0_ADDR ((uint8_t)0x53)
	IRQ_MASK0 register. More...

#define	FAST_RX_TIMER_ADDR ((uint8_t)0x54)
	FAST_RX_TIMER register. More...

#define	PA_POWER8_ADDR ((uint8_t)0x5A)
	PA_POWER8 register. More...

#define	PA_POWER7_ADDR ((uint8_t)0x5B)
	PA_POWER7 register. More...

#define	PA_POWER6_ADDR ((uint8_t)0x5C)
	PA_POWER6 register. More...

#define	PA_POWER5_ADDR ((uint8_t)0x5D)
	PA_POWER5 register. More...

#define	PA_POWER4_ADDR ((uint8_t)0x5E)
	PA_POWER4 register. More...

#define	PA_POWER3_ADDR ((uint8_t)0x5F)
	PA_POWER3 register. More...

#define	PA_POWER2_ADDR ((uint8_t)0x60)
	PA_POWER2 register. More...

#define	PA_POWER1_ADDR ((uint8_t)0x61)
	PA_POWER1 register. More...

#define	PA_POWER0_ADDR ((uint8_t)0x62)
	PA_POWER0 register. More...

#define	PA_CONFIG1_ADDR ((uint8_t)0x63)
	PA_CONFIG1 register. More...

#define	SYNTH_CONFIG2_ADDR ((uint8_t)0x65)
	SYNTH_CONFIG2 register. More...

#define	VCO_CONFIG_ADDR ((uint8_t)0x68)
	VCO_CONFIG register. More...

#define	VCO_CALIBR_IN2_ADDR ((uint8_t)0x69)
	VCO_CALIBR_IN2 register. More...

#define	VCO_CALIBR_IN1_ADDR ((uint8_t)0x6A)
	VCO_CALIBR_IN1 register. More...

#define	VCO_CALIBR_IN0_ADDR ((uint8_t)0x6B)
	VCO_CALIBR_IN0 register. More...

#define	XO_RCO_CONF1_ADDR ((uint8_t)0x6C)
	XO_RCO_CONF1 register. More...

#define	XO_RCO_CONF0_ADDR ((uint8_t)0x6D)
	XO_RCO_CONF0 register. More...

#define	RCO_CALIBR_CONF3_ADDR ((uint8_t)0x6E)
	RCO_CALIBR_CONF3 register. More...

#define	RCO_CALIBR_CONF2_ADDR ((uint8_t)0x6F)
	RCO_CALIBR_CONF2 register. More...

#define	PM_CONF4_ADDR ((uint8_t)0x75)
	PM_CONF4 register. More...

#define	PM_CONF3_ADDR ((uint8_t)0x76)
	PM_CONF3 register. More...

#define	PM_CONF2_ADDR ((uint8_t)0x77)
	PM_CONF2 register. More...

#define	PM_CONF1_ADDR ((uint8_t)0x78)
	PM_CONF1 register. More...

#define	PM_CONF0_ADDR ((uint8_t)0x79)
	PM_CONF0 register. More...

#define	MC_STATE1_ADDR ((uint8_t)0x8D)
	MC_STATE1 register. More...

#define	MC_STATE0_ADDR ((uint8_t)0x8E)
	MC_STATE0 register. More...

#define	TX_FIFO_STATUS_ADDR ((uint8_t)0x8F)
	TX_FIFO_STATUS register. More...

#define	RX_FIFO_STATUS_ADDR ((uint8_t)0x90)
	RX_FIFO_STATUS register. More...

#define	RCO_CALIBR_OUT4_ADDR ((uint8_t)0x94)
	RCO_CALIBR_OUT4 register. More...

#define	RCO_CALIBR_OUT3_ADDR ((uint8_t)0x95)
	RCO_CALIBR_OUT3 register. More...

#define	VCO_CALIBR_OUT1_ADDR ((uint8_t)0x99)
	VCO_CALIBR_OUT1 register. More...

#define	VCO_CALIBR_OUT0_ADDR ((uint8_t)0x9A)
	VCO_CALIBR_OUT0 register. More...

#define	TX_PCKT_INFO_ADDR ((uint8_t)0x9C)
	TX_PCKT_INFO register. More...

#define	RX_PCKT_INFO_ADDR ((uint8_t)0x9D)
	RX_PCKT_INFO register. More...

#define	AFC_CORR_ADDR ((uint8_t)0x9E)
	AFC_CORR register. More...

#define	LINK_QUALIF2_ADDR ((uint8_t)0x9F)
	LINK_QUALIF2 register. More...

#define	LINK_QUALIF1_ADDR ((uint8_t)0xA0)
	LINK_QUALIF1 register. More...

#define	RSSI_LEVEL_ADDR ((uint8_t)0xA2)
	RSSI_LEVEL register. More...

#define	RX_PCKT_LEN1_ADDR ((uint8_t)0xA4)
	RX_PCKT_LEN1 register. More...

#define	RX_PCKT_LEN0_ADDR ((uint8_t)0xA5)
	RX_PCKT_LEN0 register. More...

#define	CRC_FIELD3_ADDR ((uint8_t)0xA6)
	CRC_FIELD3 register. More...

#define	CRC_FIELD2_ADDR ((uint8_t)0xA7)
	CRC_FIELD2 register. More...

#define	CRC_FIELD1_ADDR ((uint8_t)0xA8)
	CRC_FIELD1 register. More...

#define	CRC_FIELD0_ADDR ((uint8_t)0xA9)
	CRC_FIELD0 register. More...

#define	RX_ADDRE_FIELD1_ADDR ((uint8_t)0xAA)
	RX_ADDRE_FIELD1 register. More...

#define	RX_ADDRE_FIELD0_ADDR ((uint8_t)0xAB)
	RX_ADDRE_FIELD0 register. More...

#define	RSSI_LEVEL_RUN_ADDR ((uint8_t)0xEF)
	RSSI_LEVEL_RUN register. More...

#define	DEVICE_INFO1_ADDR ((uint8_t)0xF0)
	DEVICE_INFO1 register. More...

#define	DEVICE_INFO0_ADDR ((uint8_t)0xF1)
	DEVICE_INFO0 register. More...

#define	IRQ_STATUS3_ADDR ((uint8_t)0xFA)
	IRQ_STATUS3 register. More...

#define	IRQ_STATUS2_ADDR ((uint8_t)0xFB)
	IRQ_STATUS2 register. More...

#define	IRQ_STATUS1_ADDR ((uint8_t)0xFC)
	IRQ_STATUS1 register. More...

#define	IRQ_STATUS0_ADDR ((uint8_t)0xFD)
	IRQ_STATUS0 register. More...

Detailed Description

Author: LowPower RF BU - AMG

Version: 1.2.1

Date: 16-April-2018

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

© COPYRIGHT 2015 STMicroelectronics

Definition in file S2LP_Regs.h.

Macro Definition Documentation

◆ AFC0_ADDR

#define AFC0_ADDR ((uint8_t)0x16)

Read and Write
Default value: 0x25
7:4 AFC_FAST_GAIN: The AFC loop gain in fast mode (2's log).
3:0 AFC_SLOW_GAIN: The AFC loop gain in slow mode (2's log).

Definition at line 339 of file S2LP_Regs.h.

◆ AFC1_ADDR

#define AFC1_ADDR ((uint8_t)0x15)

Read and Write
Default value: 0x18
7:0 AFC_FAST_PERIOD: The length of the AFC fast period.

Definition at line 325 of file S2LP_Regs.h.

◆ AFC2_ADDR

#define AFC2_ADDR ((uint8_t)0x14)

Read and Write
Default value: 0xC8
7 AFC_FREEZE_ON_SYNC: 1: enable the freeze AFC correction upon sync word detection.
6 AFC_ENABLED: 1: enable the AFC correction.
5 AFC_MODE: Select AFC mode:,  0: AFC loop closed on slicer,  1: AFC loop closed on second conversion stage.
4:0 RESERVED: -

Definition at line 310 of file S2LP_Regs.h.

◆ AFC_CORR_ADDR

#define AFC_CORR_ADDR ((uint8_t)0x9E)

Read only
Default value: 0x00
7:0 AFC_CORR: AFC corrected value.

Definition at line 1615 of file S2LP_Regs.h.

◆ ANT_SELECT_CONF_ADDR

#define ANT_SELECT_CONF_ADDR ((uint8_t)0x1F)

Read and Write
Default value: 0x45
RESERVED: -
5 EQU_CTRL: ISI cancellation equalizer:,  00: equalization disabled,  01: single pass equalization,  10: dual pass equalization.
CS_BLANKING: Do not fill the RX FIFO with data if the CS is above threhold.
AS_ENABLE: 1: enable the antenna switching.
0 AS_MEAS_TIME: Set the measurement time.

Definition at line 386 of file S2LP_Regs.h.

◆ CH_SPACE_ADDR

#define CH_SPACE_ADDR ((uint8_t)0x0C)

Read and Write
Default value: 0x3F
7:0 CH_SPACE: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps, default 100kHz.

Definition at line 193 of file S2LP_Regs.h.

◆ CHFLT_ADDR

#define CHFLT_ADDR ((uint8_t)0x13)

Read and Write
Default value: 0x23
7:4 CHFLT_M: The mantissa value of the receiver channel filter, default 100 kHz.
3:0 CHFLT_E: The exponent value of the receiver channel filter, default 100 kHz.

Definition at line 293 of file S2LP_Regs.h.

◆ CHNUM_ADDR

#define CHNUM_ADDR ((uint8_t)0x0D)

Read and Write
Default value: 0x00
7:0 CH_NUM: Channel number. This value is multiplied by the channel spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency.

Definition at line 206 of file S2LP_Regs.h.

◆ CLOCKREC0_ADDR

#define CLOCKREC0_ADDR ((uint8_t)0x21)

Read and Write
Default value: 0x58
7:5 CLK_REC_P_GAIN_FAST: Clock recovery fast loop gain (log2).
4 PSTFLT_LEN: Select the post filter length: 0: 8 symbols, 1: 16 symbols.
3:0 CLK_REC_I_GAIN_FAST: Set the integral fast gain for symbol timing recovery (PLL mode only)..

Definition at line 421 of file S2LP_Regs.h.

◆ CLOCKREC1_ADDR

#define CLOCKREC1_ADDR ((uint8_t)0x20)

Read and Write
Default value: 0x00
7:5 CLK_REC_P_GAIN_SLOW: Clock recovery slow loop gain (log2).
4 CLK_REC_ALGO_SEL: Select the symbol timing recovery algorithm: 0: DLL, 1: PLL.
3:0 CLK_REC_I_GAIN_SLOW: Set the integral slow gain for symbol timing recovery (PLL mode only).

Definition at line 404 of file S2LP_Regs.h.

◆ CRC_FIELD0_ADDR

#define CRC_FIELD0_ADDR ((uint8_t)0xA9)

Read only
Default value: 0x00
7:0 CRC_FIELD0: CRC field 0 of the received packet.

Definition at line 1734 of file S2LP_Regs.h.

◆ CRC_FIELD1_ADDR

#define CRC_FIELD1_ADDR ((uint8_t)0xA8)

Read only
Default value: 0x00
7:0 CRC_FIELD1: CRC field 1 of the received packet.

Definition at line 1721 of file S2LP_Regs.h.

◆ CRC_FIELD2_ADDR

#define CRC_FIELD2_ADDR ((uint8_t)0xA7)

Read only
Default value: 0x00
7:0 CRC_FIELD2: CRC field 2 of the received packet.

Definition at line 1708 of file S2LP_Regs.h.

◆ CRC_FIELD3_ADDR

#define CRC_FIELD3_ADDR ((uint8_t)0xA6)

Read only
Default value: 0x00
7:0 CRC_FIELD3: CRC field 3 of the received packet.

Definition at line 1695 of file S2LP_Regs.h.

◆ CSMA_CONF0_ADDR

#define CSMA_CONF0_ADDR ((uint8_t)0x4F)

Read and Write
Default value: 0x00
7:4 CCA_LEN: The number of time in which the listen operation is performed.
3 RESERVED: -
2:0 NBACKOFF_MAX: Max number of back-off cycles.

Definition at line 992 of file S2LP_Regs.h.

◆ CSMA_CONF1_ADDR

#define CSMA_CONF1_ADDR ((uint8_t)0x4E)

Read and Write
Default value: 0x04
7:2 BU_PRSC: Prescaler value for the back-off unit BU.
1:0 CCA_PERIOD: Multiplier for the Tcca timer.

Definition at line 976 of file S2LP_Regs.h.

◆ CSMA_CONF2_ADDR

#define CSMA_CONF2_ADDR ((uint8_t)0x4D)

Read and Write
Default value: 0x00
7:0 BU_CNTR_SEED[7:0]: LSB part of the seed for the random generator used to apply the CSMA algorithm.

Definition at line 962 of file S2LP_Regs.h.

◆ CSMA_CONF3_ADDR

#define CSMA_CONF3_ADDR ((uint8_t)0x4C)

Read and Write
Default value: 0x4C
7:0 BU_CNTR_SEED[14:8]: MSB part of the seed for the random generator used to apply the CSMA algorithm.

Definition at line 949 of file S2LP_Regs.h.

◆ DEVICE_INFO0_ADDR

#define DEVICE_INFO0_ADDR ((uint8_t)0xF1)

Read only
Default value: 0x41
7:0 RSSI_LEVEL: S2-LP version number

Definition at line 1799 of file S2LP_Regs.h.

◆ DEVICE_INFO1_ADDR

#define DEVICE_INFO1_ADDR ((uint8_t)0xF0)

Read only
Default value: 0x00
7:0 PARTNUM: S2-LP part number

Definition at line 1786 of file S2LP_Regs.h.

◆ FAST_RX_TIMER_ADDR

#define FAST_RX_TIMER_ADDR ((uint8_t)0x54)

Read and Write
Default value: 0x00
7:0 RSSI_SETTLING_LIMIT[7:0]: RSSI settling limit word. This determines the duration of the
                     FAST_RX_TERM timer.

Definition at line 1059 of file S2LP_Regs.h.

◆ FIFO_CONFIG0_ADDR

#define FIFO_CONFIG0_ADDR ((uint8_t)0x3F)

Read and Write
Default value: 0x30
7 RESERVED: -
6:0 TX_AETHR: Set the TX FIFO almost empty threshold.

Definition at line 768 of file S2LP_Regs.h.

◆ FIFO_CONFIG1_ADDR

#define FIFO_CONFIG1_ADDR ((uint8_t)0x3E)

Read and Write
Default value: 0x30
7 RESERVED: -
6:0 TX_AFTHR: Set the TX FIFO almost full threshold.

Definition at line 754 of file S2LP_Regs.h.

◆ FIFO_CONFIG2_ADDR

#define FIFO_CONFIG2_ADDR ((uint8_t)0x3D)

Read and Write
Default value: 0x30
7 RESERVED: -
6:0 RX_AETHR: Set the RX FIFO almost empty threshold.

Definition at line 740 of file S2LP_Regs.h.

◆ FIFO_CONFIG3_ADDR

#define FIFO_CONFIG3_ADDR ((uint8_t)0x3C)

Read and Write
Default value: 0x30
7 RESERVED: -
6:0 RX_AFTHR: Set the RX FIFO almost full threshold.

Definition at line 726 of file S2LP_Regs.h.

◆ GPIO0_CONF_ADDR

#define GPIO0_CONF_ADDR ((uint8_t)0x00)

Read and Write
Default value: 0x0A
7:3 GPIO_SELECT: Specify the GPIO0 I/O signal, default setting POR.
2 RESERVED: -
1:0 GPIO_MODE: GPIO0 Mode:,  01b: Digital Input,  10b: Digital Output Low Power,  11b: Digital Output High Power

Definition at line 30 of file S2LP_Regs.h.

◆ GPIO1_CONF_ADDR

#define GPIO1_CONF_ADDR ((uint8_t)0x01)

Read and Write
Default value: 0xA2
7:3 GPIO_SELECT: Specify the GPIO1 I/O signal, default setting digital GND.
2 RESERVED: -
1:0 GPIO_MODE: GPIO1 Mode:,  01b: Digital Input1,  0b: Digital Output Low Power,  11b: Digital Output High Power

Definition at line 46 of file S2LP_Regs.h.

◆ GPIO2_CONF_ADDR

#define GPIO2_CONF_ADDR ((uint8_t)0x02)

Read and Write
Default value: 0xA2
7:3 GPIO_SELECT: Specify the GPIO2 I/O signal, default setting digital GND.
2 RESERVED: -
1:0 GPIO_MODE: GPIO2 Mode:,  01b: Digital Input,  10b: Digital Output Low Power,  11b: Digital Output High Power

Definition at line 62 of file S2LP_Regs.h.

◆ GPIO3_CONF_ADDR

#define GPIO3_CONF_ADDR ((uint8_t)0x03)

Read and Write
Default value: 0xA2
7:3 GPIO_SELECT: Specify the GPIO3 I/O signal, default setting digital GND.
2 RESERVED: -
1:0 GPIO_MODE: GPIO3 Mode:,  00b: Analog,  01b: Digital Input,  10b: Digital Output Low Power,  11b: Digital Output High Power

Definition at line 78 of file S2LP_Regs.h.

◆ IF_OFFSET_ANA_ADDR

#define IF_OFFSET_ANA_ADDR ((uint8_t)0x09)

Read and Write
Default value: 0x2A
7:0 IF_OFFSET_ANA: Intermediate frequency setting for the analog RF synthesizer, default: 300 kHz.

Definition at line 167 of file S2LP_Regs.h.

◆ IF_OFFSET_DIG_ADDR

#define IF_OFFSET_DIG_ADDR ((uint8_t)0x0A)

Read and Write
Default value: 0xB8
7:0 IF_OFFSET_DIG: Intermediate frequency setting for the digital shift-to-baseband circuits, default: 300 kHz.

Definition at line 180 of file S2LP_Regs.h.

◆ IRQ_MASK0_ADDR

#define IRQ_MASK0_ADDR ((uint8_t)0x53)

Read and Write
Default value: 0x00
7:0 INT_MASK[7:0]: Enable the routing of the interrupt flag on the configured IRQ GPIO.

Definition at line 1045 of file S2LP_Regs.h.

◆ IRQ_MASK1_ADDR

#define IRQ_MASK1_ADDR ((uint8_t)0x52)

Read and Write
Default value: 0x00
7:0 INT_MASK[15:8]: Enable the routing of the interrupt flag on the configured IRQ GPIO.

Definition at line 1032 of file S2LP_Regs.h.

◆ IRQ_MASK2_ADDR

#define IRQ_MASK2_ADDR ((uint8_t)0x51)

Read and Write
Default value: 0x00
7:0 INT_MASK[23:16]: Enable the routing of the interrupt flag on the configured IRQ GPIO.

Definition at line 1019 of file S2LP_Regs.h.

◆ IRQ_MASK3_ADDR

#define IRQ_MASK3_ADDR ((uint8_t)0x50)

Read and Write
Default value: 0x00
7:0 INT_MASK[31:24]: Enable the routing of the interrupt flag on the configured IRQ GPIO.

Definition at line 1006 of file S2LP_Regs.h.

◆ IRQ_STATUS0_ADDR

#define IRQ_STATUS0_ADDR ((uint8_t)0xFD)

Read only
Default value: 0x00
7:0 INT_LEVEL[7:0]: Interrupt status register 0

Definition at line 1851 of file S2LP_Regs.h.

◆ IRQ_STATUS1_ADDR

#define IRQ_STATUS1_ADDR ((uint8_t)0xFC)

Read only
Default value: 0x05
7:0 INT_LEVEL[15:8]: Interrupt status register 1

Definition at line 1838 of file S2LP_Regs.h.

◆ IRQ_STATUS2_ADDR

#define IRQ_STATUS2_ADDR ((uint8_t)0xFB)

Read only
Default value: 0x09
7:0 INT_LEVEL[23:16]: Interrupt status register 2

Definition at line 1825 of file S2LP_Regs.h.

◆ IRQ_STATUS3_ADDR

#define IRQ_STATUS3_ADDR ((uint8_t)0xFA)

Read only
Default value: 0x00
7:0 INT_LEVEL[31:24]: Interrupt status register 3

Definition at line 1812 of file S2LP_Regs.h.

◆ LINK_QUALIF1_ADDR

#define LINK_QUALIF1_ADDR ((uint8_t)0xA0)

Read only
Default value: 0x00
7 CS: Carrier Sense indication.
6:0 SQI: SQI value of the recived packet.

Definition at line 1642 of file S2LP_Regs.h.

◆ LINK_QUALIF2_ADDR

#define LINK_QUALIF2_ADDR ((uint8_t)0x9F)

Read only
Default value: 0x00
7:0 PQI: PQI value of the received packet.

Definition at line 1628 of file S2LP_Regs.h.

◆ MC_STATE0_ADDR

#define MC_STATE0_ADDR ((uint8_t)0x8E)

Read only
Default value: 0x07
7:1 STATE: Current state.
0 XO_ON: 1: XO is operating.

Definition at line 1484 of file S2LP_Regs.h.

◆ MC_STATE1_ADDR

#define MC_STATE1_ADDR ((uint8_t)0x8D)

Read only
Default value: 0x52
5 RESERVED: -
RCO_CAL_OK: RCO calibration succesfully terminated.
ANT_SEL: Currently selected antenna.
TX_FIFO_FULL: 1: TX FIFO is full.
RX_FIFO_EMPTY: 1: RX FIFO is empty.
ERROR_LOCK: 1: RCO calibrator error.

Definition at line 1466 of file S2LP_Regs.h.

◆ MCU_CK_CONF_ADDR

#define MCU_CK_CONF_ADDR ((uint8_t)0x04)

Read and Write
Default value: 0x00
7 EN_MCU_CLK: 1: The internal divider logic is running, so the MCU clock is available (but proper GPIO configuration is needed)
6:5 CLOCK_TAIL: Number of extra clock cycles provided to the MCU before switching to STANDBY state.,  00b: 0 extra clock cycle,  01b: 64 extra clock cycles,  10b: 256 extra clock cycles,  11b: 512 extra clock cycles
4:1 XO_RATIO: Divider for the XO clock output
0 RCO_RATIO: Divider for the RCO clock output,  0: 1 , 1: 1/128

Definition at line 95 of file S2LP_Regs.h.

◆ MOD0_ADDR

#define MOD0_ADDR ((uint8_t)0x12)

Read and Write
Default value: 0x93
7:0 FDEV_M: The mantissa value of the frequency deviation equation, default 20 kHz.

Definition at line 279 of file S2LP_Regs.h.

◆ MOD1_ADDR

#define MOD1_ADDR ((uint8_t)0x11)

Read and Write
Default value: 0x03
7 PA_INTERP_EN: 1: enable the power interpolator
6 MOD_INTERP_EN: 1: enable frequency interpolator
5:4 G4FSK_CONST_MAP: Select the constellation map for 4-GFSK.
3:0 FDEV_E: The exponent value of the frequency deviation equation, default 20 kHz.

Definition at line 263 of file S2LP_Regs.h.

◆ MOD2_ADDR

#define MOD2_ADDR ((uint8_t)0x10)

Read and Write
Default value: 0x77
7:4 MOD_TYPE: Modulation type:,  0: 2-FSK,  1: 4-FSK,  2: 2-GFSK BT=1,  3: 4-GFSK BT=1,  5: ASK/OOK,  7: unmodulated,  10: 2-GFSK BT=0.5,  12: 4-GFSK BT=0.5
3:0 DATARATE_E: The exponent value of the data rate equation, default 38.4 ksps.

Definition at line 246 of file S2LP_Regs.h.

◆ MOD3_ADDR

#define MOD3_ADDR ((uint8_t)0x0F)

Read and Write
Default value: 0x2B
7:0 DATARATE_M[7:0]: The LSB of the mantissa value of the data rate equation, default 38.4 ksps.

Definition at line 232 of file S2LP_Regs.h.

◆ MOD4_ADDR

#define MOD4_ADDR ((uint8_t)0x0E)

Read and Write
Default value: 0x83
7:0 DATARATE_M[15:8]: The MSB of the mantissa value of the data rate equation, default 38.4 ksps.

Definition at line 219 of file S2LP_Regs.h.

◆ PA_CONFIG1_ADDR

#define PA_CONFIG1_ADDR ((uint8_t)0x63)

Read and Write
Default value: 0x03
5 RESERVED: -
LIN_NLOG: 1: enable the linear-to-log conversion of the PA code output.
2 FIR_CFG: FIR configuration: 00b: filtering, 01b : ramping, 10b: switching.
FIR_EN: 1: enable FIR.
RESERVED: -

Definition at line 1209 of file S2LP_Regs.h.

◆ PA_POWER0_ADDR

#define PA_POWER0_ADDR ((uint8_t)0x62)

Read and Write
Default value: 0x47
DIG_SMOOTH_EN: 1: enable the generation of the internal signal TX_DATA which is the input of the FIR.
PA_MAXDBM: 1: configure the PA to send maximum output power.
PA_RAMP_EN: 1: enable the power ramping
3 PA_RAMP_STEP_LEN: Set the step width (unit: 1/8 of bit period).
0 PA_LEVEL_MAX_IDX: Final level for power ramping or selected output power index.

Definition at line 1188 of file S2LP_Regs.h.

◆ PA_POWER1_ADDR

#define PA_POWER1_ADDR ((uint8_t)0x61)

Read and Write
Default value: 0x00
7 RESERVED: -
6:0 PA_LEVEL_1: Output power level for 1st slot.

Definition at line 1171 of file S2LP_Regs.h.

◆ PA_POWER2_ADDR

#define PA_POWER2_ADDR ((uint8_t)0x60)

Read and Write
Default value: 0x60
7 RESERVED: -
6:0 PA_LEVEL_2: Output power level for 2nd slot.

Definition at line 1157 of file S2LP_Regs.h.

◆ PA_POWER3_ADDR

#define PA_POWER3_ADDR ((uint8_t)0x5F)

Read and Write
Default value: 0x48
7 RESERVED: -
6:0 PA_LEVEL_3: Output power level for 3rd slot.

Definition at line 1143 of file S2LP_Regs.h.

◆ PA_POWER4_ADDR

#define PA_POWER4_ADDR ((uint8_t)0x5E)

Read and Write
Default value: 0x30
7 RESERVED: -
6:0 PA_LEVEL_4: Output power level for 4th slot.

Definition at line 1129 of file S2LP_Regs.h.

◆ PA_POWER5_ADDR

#define PA_POWER5_ADDR ((uint8_t)0x5D)

Read and Write
Default value: 0x24
7 RESERVED: -
6:0 PA_LEVEL_5: Output power level for 5th slot.

Definition at line 1115 of file S2LP_Regs.h.

◆ PA_POWER6_ADDR

#define PA_POWER6_ADDR ((uint8_t)0x5C)

Read and Write
Default value: 0x18
7 RESERVED: -
6:0 PA_LEVEL_6: Output power level for 6th slot.

Definition at line 1101 of file S2LP_Regs.h.

◆ PA_POWER7_ADDR

#define PA_POWER7_ADDR ((uint8_t)0x5B)

Read and Write
Default value: 0x0C
7 RESERVED: -
6:0 PA_LEVEL_7: Output power level for 7th slot.

Definition at line 1087 of file S2LP_Regs.h.

◆ PA_POWER8_ADDR

#define PA_POWER8_ADDR ((uint8_t)0x5A)

Read and Write
Default value: 0x01
7 RESERVED: -
6:0 PA_LEVEL8: Output power level for 8th slot.

Definition at line 1073 of file S2LP_Regs.h.

◆ PCKT_FLT_GOALS0_ADDR

#define PCKT_FLT_GOALS0_ADDR ((uint8_t)0x45)

Read and Write
Default value: 0x00
7:0 TX_SOURCE_ADDR: Tx packet source or RX packet destination field.

Definition at line 858 of file S2LP_Regs.h.

◆ PCKT_FLT_GOALS1_ADDR

#define PCKT_FLT_GOALS1_ADDR ((uint8_t)0x44)

Read and Write
Default value: 0x00
7:0 MULTICAST_ADDR/DUAL_SYNC0: If dual sync mode enabled: dual SYNC word byte 0., Multicast address.

Definition at line 845 of file S2LP_Regs.h.

◆ PCKT_FLT_GOALS2_ADDR

#define PCKT_FLT_GOALS2_ADDR ((uint8_t)0x43)

Read and Write
Default value: 0x00
7:0 BROADCAST_ADDR/DUAL_SYNC1: If dual sync mode enabled: dual SYNC word byte 1., Broadcast address.

Definition at line 832 of file S2LP_Regs.h.

◆ PCKT_FLT_GOALS3_ADDR

#define PCKT_FLT_GOALS3_ADDR ((uint8_t)0x42)

Read and Write
Default value: 0x00
7:0 RX_SOURCE_ADDR/DUAL_SYNC2: If dual sync mode enabled: dual SYNC word byte 2., Otherwise RX packet source or TX packet destination field.

Definition at line 819 of file S2LP_Regs.h.

◆ PCKT_FLT_GOALS4_ADDR

#define PCKT_FLT_GOALS4_ADDR ((uint8_t)0x41)

Read and Write
Default value: 0x00
7:0 RX_SOURCE_MASK/DUAL_SYNC3: If dual sync mode enabled: dual SYNC word byte 3., Otherwise mask register for source affress filtering.

Definition at line 806 of file S2LP_Regs.h.

◆ PCKT_FLT_OPTIONS_ADDR

#define PCKT_FLT_OPTIONS_ADDR ((uint8_t)0x40)

Read and Write
Default value: 0x40
RESERVED: -
RX_TIMEOUT_AND_OR_SEL: Logical boolean function applied to CS/SQI/PQI values: 1: OR, 0: AND.
RESERVED: -
SOURCE_ADDR_FLT: 1: RX packet accepted if its source field matches with RX_SOURCE_ADDR register
DEST_VS_BROADCAST_ADDR: 1: RX packet accepted if its source field matches with BROADCAST_ADDR register.
DEST_VS_MULTICAST_ADDR: 1: RX packet accepted if its destination address matches with MULTICAST_ADDR register.
DEST_VS_SOURCE_ADDR: 1: RX packet accepted if its destination address matches with RX_SOURCE_ADDR register.
CRC_FLT: 1: packet discarded if CRC is not valid.

Definition at line 788 of file S2LP_Regs.h.

◆ PCKT_PSTMBL_ADDR

#define PCKT_PSTMBL_ADDR ((uint8_t)0x38)

Read and Write
Default value: 0x00
7:0 PCKT_PSTMBL: Set the packet postamble length.

Definition at line 642 of file S2LP_Regs.h.

◆ PCKTCTRL1_ADDR

#define PCKTCTRL1_ADDR ((uint8_t)0x30)

Read and Write
Default value: 0x2C
5 CRC_MODE: CRC field:,  0: no CRC field,  1: CRC using poly 0x07,  2: CRC using poly 0x8005,  3: CRC using poly 0x1021,  4: CRC using poly 0x864CBF
WHIT_EN: 1: enable the whitening mode.
2 TXSOURCE: Tx source data:,  0: normal mode,  1: direct through FIFO,  2: direct through GPIO,  3: PN9
SECOND_SYNC_SEL: In TX mode: 0 select the primary SYNC word, 1 select the secondary SYNC word., In RX mode: enable the dual SYNC word detection mode.
FEC_EN: 1: enable the FEC encoding in TX or the Viterbi decoding in RX.

Definition at line 530 of file S2LP_Regs.h.

◆ PCKTCTRL2_ADDR

#define PCKTCTRL2_ADDR ((uint8_t)0x2F)

Read and Write
Default value: 0x00
6 RESERVED: -
FCS_TYPE_4G: FCS type in header field of 802.15.4g packet.
FEC_TYPE_4G: Select the FEC type of 802.15.4g packet: 0: NRNSC. 1: RSC.
INT_EN_4G: 1: enable the interleaving of 802.15.4g packet.
MBUS_3OF6_EN: 1: enable the 3-out-of-6 encoding/decoding.
MANCHESTER_EN: 1: enable the Manchester encoding/decoding.
FIX_VAR_LEN: Packet length mode:,  0: fixed,  1: variable (in variable mode the field LEN_WID of PCKTCTRL3 register must be configured)

Definition at line 508 of file S2LP_Regs.h.

◆ PCKTCTRL3_ADDR

#define PCKTCTRL3_ADDR ((uint8_t)0x2E)

Read and Write
Default value: 0x20
6 PCKT_FRMT: Format of packet:,  0: Basic,  2: WM-Bus,  3: STack
4 RX_MODE: RX mode:,  0: normal mode,  1: direct through FIFO,  2: direct through GPIO
FSK4_SYM_SWAP: Select the symbol mapping for 4(G)FSK.
BYTE_SWAP: Select the transmission order between MSB and LSB.
0 PREAMBLE_SEL: Select the preamble pattern between '10' and '01'.

Definition at line 485 of file S2LP_Regs.h.

◆ PCKTCTRL4_ADDR

#define PCKTCTRL4_ADDR ((uint8_t)0x2D)

Read and Write
Default value: 0x00
7 LEN_WID: The number of bytes used for the length field: 0: 1 byte, 1: 2 bytes.
6:4 RESERVED: -
3 ADDRESS_LEN: 1: include the ADDRESS field in the packet.
2:0 RESERVED: -

Definition at line 467 of file S2LP_Regs.h.

◆ PCKTCTRL5_ADDR

#define PCKTCTRL5_ADDR ((uint8_t)0x2C)

Read and Write
Default value: 0x10
7:0 PREAMBLE_LEN[7:0]: The LSB of the number of '01 or '10' of the preamble of the packet.

Definition at line 451 of file S2LP_Regs.h.

◆ PCKTCTRL6_ADDR

#define PCKTCTRL6_ADDR ((uint8_t)0x2B)

Read and Write
Default value: 0x80
7:2 SYNC_LEN: The number of bits used for the SYNC field in the packet.
1:0 PREAMBLE_LEN_9_8: The MSB of the number of '01 or '10' of the preamble of the packet.

Definition at line 437 of file S2LP_Regs.h.

◆ PCKTLEN0_ADDR

#define PCKTLEN0_ADDR ((uint8_t)0x32)

Read and Write
Default value: 0x14
7:0 PCKTLEN0: LSB of length of packet in bytes.

Definition at line 560 of file S2LP_Regs.h.

◆ PCKTLEN1_ADDR

#define PCKTLEN1_ADDR ((uint8_t)0x31)

Read and Write
Default value: 0x00
7:0 PCKTLEN1: MSB of length of packet in bytes.

Definition at line 547 of file S2LP_Regs.h.

◆ PM_CONF0_ADDR

#define PM_CONF0_ADDR ((uint8_t)0x79)

Read and Write
Default value: 0x42
RESERVED: -
4 SET_SMPS_LVL: 000: SMPS output voltage 1.1 V, 001: SMPS output voltage 1.2 V, 010: SMPS output voltage 1.3 V, 011: SMPS output voltage 1.4 V, 100: SMPS output voltage 1.5 V, 101: SMPS output voltage 1.6 V, 110: SMPS output voltage 1.7 V, 111: SMPS output voltage 1.8 V.
2 RESERVED: -
RESERVED: -
SLEEP_MODE_SEL: 0: SLEEP without FIFO retention; 1: SLEEP with FIFO retention.

Definition at line 1447 of file S2LP_Regs.h.

◆ PM_CONF1_ADDR

#define PM_CONF1_ADDR ((uint8_t)0x78)

Read and Write
Default value: 0x39
RESERVED: -
BATTERY_LVL_EN: 1: enable battery level detector circuit.
4 SET_BLD_TH: Set the BLD threshold: 00b: 2.7V, 01b: 2.5V, 10b: 2.3V, 00b: 2.1V.
RESERVED: -
RESERVED: -
RESERVED: -
RESERVED: -

Definition at line 1429 of file S2LP_Regs.h.

◆ PM_CONF2_ADDR

#define PM_CONF2_ADDR ((uint8_t)0x77)

Read and Write
Default value: 0x00
7:0 KRM[7:0]: Sets the divider ratio (LSB) of the rate multiplier (default: FSW=FCLK/4)

Definition at line 1410 of file S2LP_Regs.h.

◆ PM_CONF3_ADDR

#define PM_CONF3_ADDR ((uint8_t)0x76)

Read and Write
Default value: 0x20
7 KRM_EN: 0: divider by 4 enabled (SMPS' switching frequency is FSW=FCLK/4), 1: rate multiplier enabled (SMPS' switching frequency is FSW=KRM*FOSC/(2^15).
6:0 KRM_14_8: Sets the divider ratio (MSB) of the rate multiplier (default: FSW=FCLK/4)

Definition at line 1396 of file S2LP_Regs.h.

◆ PM_CONF4_ADDR

#define PM_CONF4_ADDR ((uint8_t)0x75)

Read and Write
Default value: 0x17
TEMP_SENSOR_EN: 1: enable the temperature sensor.
TEMP_SENS_BUFF_EN: 1: enable the output buffer for the temperature sensor.
EXT_SMPS: 1: disable the internal SMPS.
RESERVED: -
RESERVED: -
RESERVED: -
0 RESERVED: -

Definition at line 1380 of file S2LP_Regs.h.

◆ PROTOCOL0_ADDR

#define PROTOCOL0_ADDR ((uint8_t)0x3B)

Read and Write
Default value: 0x08
4 NMAX_RETX: Max. number of re-TX (from 0 to 15)(0: re-transmission is not performed).
NACK_TX: 1: field NO_ACK=1 on transmitted packet.
AUTO_ACK: 1: enable the automatic acknowledgement if packet received request.
PERS_RX: 1: enable the persistent RX mode.
RESERVED: -

Definition at line 709 of file S2LP_Regs.h.

◆ PROTOCOL1_ADDR

#define PROTOCOL1_ADDR ((uint8_t)0x3A)

Read and Write
Default value: 0x00
LDC_MODE: 1: enable the Low Duty Cycle mode.
LDC_RELOAD_ON_SYNC: 1: enable the LDC timer reload mode.
PIGGYBACKING: 1: enable the piggybacking.
FAST_CS_TERM_EN: 1: enable the RX sniff timer.
SEED_RELOAD: 1: enable the reload of the back-off random generator seed using the value written in the BU_COUNTER_SEED.
CSMA_ON: 1 enable the CSMA channel access mode.
CSMA_PERS_ON: 1: enable the CSMA persistent mode (no backoff cycles).
AUTO_PCKT_FLT: 1: enable the automatic packet filtering control.

Definition at line 685 of file S2LP_Regs.h.

◆ PROTOCOL2_ADDR

#define PROTOCOL2_ADDR ((uint8_t)0x39)

Read and Write
Default value: 0x40
CS_TIMEOUT_MASK: 1: enable the CS value contributes to timeout disabling.
SQI_TIMEOUT_MASK: 1: enable the SQI value contributes to timeout disabling.
PQI_TIMEOUT_MASK: 1: enable the PQI value contributes to timeout disabling.
3 TX_SEQ_NUM_RELOAD: TX sequence number to be used when counting reset is required using the related command.
FIFO_GPIO_OUT_MUX_SEL: 1: select the almost empty/full control for TX FIFO., 0: select the almost empty/full control for RX FIFO.
0 LDC_TIMER_MULT: Set the LDC timer multiplier factor: 00b: x1, 01b: x2, 10b: x4, 11b: x8.

Definition at line 660 of file S2LP_Regs.h.

◆ QI_ADDR

#define QI_ADDR ((uint8_t)0x37)

Read and Write
Default value: 0x01
7:5 SQI_TH: SQI threshold.
4:1 PQI_TH: PQI threshold.
0 SQI_EN: 1: enable the SQI check.

Definition at line 627 of file S2LP_Regs.h.

◆ RCO_CALIBR_CONF2_ADDR

#define RCO_CALIBR_CONF2_ADDR ((uint8_t)0x6F)

Read and Write
Default value: 0x4D
RFB_IN[0]: LSB part of RFB word value for RCO.
4 RESERVED: -
4 RESERVED: -
RESERVED: -
0 RESERVED: -

Definition at line 1361 of file S2LP_Regs.h.

◆ RCO_CALIBR_CONF3_ADDR

#define RCO_CALIBR_CONF3_ADDR ((uint8_t)0x6E)

Read and Write
Default value: 0x70
7:4 RWT_IN: RWT word value for the RCO.
3:0 RFB_IN_4_1: MSB part of RFB word value for RCO.

Definition at line 1343 of file S2LP_Regs.h.

◆ RCO_CALIBR_OUT3_ADDR

#define RCO_CALIBR_OUT3_ADDR ((uint8_t)0x95)

Read only
Default value: 0x00
7 RFB_OUT[0]: RFT word (LSB) from internal RCO calibrator.
6:0 RESERVED: -

Definition at line 1542 of file S2LP_Regs.h.

◆ RCO_CALIBR_OUT4_ADDR

#define RCO_CALIBR_OUT4_ADDR ((uint8_t)0x94)

Read only
Default value: 0x70
7:4 RWT_OUT: RWT word from internal RCO calibrator.
3:0 RFB_OUT_4_1: RFT word (MSB) from internal RCO calibrator.

Definition at line 1527 of file S2LP_Regs.h.

◆ RSSI_FLT_ADDR

#define RSSI_FLT_ADDR ((uint8_t)0x17)

Read and Write
Default value: 0xE3
7:4 RSSI_FLT: Gain of the RSSI filter.
3:2 CS_MODE: Carrier sense mode:,  00b: Static CS,  01b: Dynamic CS with 6dB dynamic threshold,  10b: Dynamic CS with 12dB dynamic threshold,  11b: Dynamic CS with 18dB dynamic threshold.
1:0 RESERVED: -

Definition at line 355 of file S2LP_Regs.h.

◆ RSSI_LEVEL_ADDR

#define RSSI_LEVEL_ADDR ((uint8_t)0xA2)

Read only
Default value: 0x00
7:0 RSSI_LEVEL: RSSI level captured at the end of the SYNC word detection of the received packet.

Definition at line 1656 of file S2LP_Regs.h.

◆ RSSI_LEVEL_RUN_ADDR

#define RSSI_LEVEL_RUN_ADDR ((uint8_t)0xEF)

Read only
Default value: 0x00
7:0 RSSI_LEVEL_RUN: RSSI level of the received packet, which supports continuos fast SPI reading.

Definition at line 1773 of file S2LP_Regs.h.

◆ RSSI_TH_ADDR

#define RSSI_TH_ADDR ((uint8_t)0x18)

Read and Write
Default value: 0x28
7:0 RSSI_TH: Signal detect threshold in 0.5 dB steps, default -120 dBm corresponds to 0x28.

Definition at line 369 of file S2LP_Regs.h.

◆ RX_ADDRE_FIELD0_ADDR

#define RX_ADDRE_FIELD0_ADDR ((uint8_t)0xAB)

Read only
Default value: 0x00
7:0 RX_ADDRE_FIELD0: Destination address field of the received packet.

Definition at line 1760 of file S2LP_Regs.h.

◆ RX_ADDRE_FIELD1_ADDR

#define RX_ADDRE_FIELD1_ADDR ((uint8_t)0xAA)

Read only
Default value: 0x00
7:0 RX_ADDRE_FIELD1: Source address field of the received packet.

Definition at line 1747 of file S2LP_Regs.h.

◆ RX_FIFO_STATUS_ADDR

#define RX_FIFO_STATUS_ADDR ((uint8_t)0x90)

Read only
Default value: 0x00
7 RESERVED: -
6:0 NELEM_RXFIFO: Number of elements in RX FIFO.

Definition at line 1513 of file S2LP_Regs.h.

◆ RX_PCKT_INFO_ADDR

#define RX_PCKT_INFO_ADDR ((uint8_t)0x9D)

Read only
Default value: 0x00
7:3 RESERVED: -
2 NACK_RX: NACK field of the received packet.
1:0 RX_SEQ_NUM: Sequence number of the received packet.

Definition at line 1601 of file S2LP_Regs.h.

◆ RX_PCKT_LEN0_ADDR

#define RX_PCKT_LEN0_ADDR ((uint8_t)0xA5)

Read only
Default value: 0x00
7:0 RX_PCKT_LEN[7:0]: LSB valueof the length of the packet received.

Definition at line 1682 of file S2LP_Regs.h.

◆ RX_PCKT_LEN1_ADDR

#define RX_PCKT_LEN1_ADDR ((uint8_t)0xA4)

Read only
Default value: 0x00
7:0 RX_PCKT_LEN[14:8]: MSB valueof the length of the packet received.

Definition at line 1669 of file S2LP_Regs.h.

◆ SYNC0_ADDR

#define SYNC0_ADDR ((uint8_t)0x36)

Read and Write
Default value: 0x88
7:0 SYNC0: SYNC word byte 0.

Definition at line 612 of file S2LP_Regs.h.

◆ SYNC1_ADDR

#define SYNC1_ADDR ((uint8_t)0x35)

Read and Write
Default value: 0x88
7:0 SYNC1: SYNC word byte 1.

Definition at line 599 of file S2LP_Regs.h.

◆ SYNC2_ADDR

#define SYNC2_ADDR ((uint8_t)0x34)

Read and Write
Default value: 0x88
7:0 SYNC2: SYNC word byte 3.

Definition at line 586 of file S2LP_Regs.h.

◆ SYNC3_ADDR

#define SYNC3_ADDR ((uint8_t)0x33)

Read and Write
Default value: 0x88
7:0 SYNC3: SYNC word byte 4.

Definition at line 573 of file S2LP_Regs.h.

◆ SYNT0_ADDR

#define SYNT0_ADDR ((uint8_t)0x08)

Read and Write
Default value: 0x62
7:0 SYNT[7:0]: LSB bits of the PLL programmable divider.

Definition at line 154 of file S2LP_Regs.h.

◆ SYNT1_ADDR

#define SYNT1_ADDR ((uint8_t)0x07)

Read and Write
Default value: 0x27
7:0 SYNT[15:8]: Intermediate bits of the PLL programmable divider.

Definition at line 141 of file S2LP_Regs.h.

◆ SYNT2_ADDR

#define SYNT2_ADDR ((uint8_t)0x06)

Read and Write
Default value: 0x16
7:0 SYNT[23:16]: Intermediate bits of the PLL programmable divider.

Definition at line 128 of file S2LP_Regs.h.

◆ SYNT3_ADDR

#define SYNT3_ADDR ((uint8_t)0x05)

Read and Write
Default value: 0x42
7:5 PLL_CP_ISEL: Set the charge pump current according to the XTAL frequency.
4 BS: Synthesizer band select. This parameter selects the out-of loop divide factor of the synthesizer:,  0: 4, band select factor for high band,  1: 8, band select factor for middle band.
3:0 SYNT_27_24: MSB bits of the PLL programmable divider.

Definition at line 113 of file S2LP_Regs.h.

◆ SYNTH_CONFIG2_ADDR

#define SYNTH_CONFIG2_ADDR ((uint8_t)0x65)

Read and Write
Default value: 0xD0
RESERVED: -
RESERVED: -
RESERVED: -
3 RESERVED: -
PLL_PFD_SPLIT_EN: Enables increased DN current pulses to improve linearization of CP/PFD.
0 RESERVED: -

Definition at line 1229 of file S2LP_Regs.h.

◆ TIMERS0_ADDR

#define TIMERS0_ADDR ((uint8_t)0x4B)

Read and Write
Default value: 0x00
7:0 LDC_RELOAD_CNTR: Counter value for reload operation of wake up timer.

Definition at line 936 of file S2LP_Regs.h.

◆ TIMERS1_ADDR

#define TIMERS1_ADDR ((uint8_t)0x4A)

Read and Write
Default value: 0x01
7:0 LDC_RELOAD_PRSC: Prescaler value for reload operation of wake up timer.

Definition at line 923 of file S2LP_Regs.h.

◆ TIMERS2_ADDR

#define TIMERS2_ADDR ((uint8_t)0x49)

Read and Write
Default value: 0x00
7:0 LDC_TIMER_CNTR: Counter for wake up timer.

Definition at line 910 of file S2LP_Regs.h.

◆ TIMERS3_ADDR

#define TIMERS3_ADDR ((uint8_t)0x48)

Read and Write
Default value: 0x01
7:0 LDC_TIMER_PRESC: Prescaler for wake up timer.

Definition at line 897 of file S2LP_Regs.h.

◆ TIMERS4_ADDR

#define TIMERS4_ADDR ((uint8_t)0x47)

Read and Write
Default value: 0x00
7:0 RX_TIMER_PRESC: Prescaler for RX timer.

Definition at line 884 of file S2LP_Regs.h.

◆ TIMERS5_ADDR

#define TIMERS5_ADDR ((uint8_t)0x46)

Read and Write
Default value: 0x01
7:0 RX_TIMER_CNTR: Counter for RX timer.

Definition at line 871 of file S2LP_Regs.h.

◆ TX_FIFO_STATUS_ADDR

#define TX_FIFO_STATUS_ADDR ((uint8_t)0x8F)

Read only
Default value: 0x00
7 RESERVED: -
6:0 NELEM_TXFIFO: Number of elements in TX FIFO.

Definition at line 1499 of file S2LP_Regs.h.

◆ TX_PCKT_INFO_ADDR

#define TX_PCKT_INFO_ADDR ((uint8_t)0x9C)

Read only
Default value: 0x00
7:6 RESERVED: -
5:4 TX_SEQ_NUM: Current TX packet sequence number.
3:0 N_RETX: Number of re-transmissions done for the last TX packet.

Definition at line 1585 of file S2LP_Regs.h.

◆ VCO_CALIBR_IN0_ADDR

#define VCO_CALIBR_IN0_ADDR ((uint8_t)0x6B)

Read and Write
Default value: 0x40
7 RESERVED: -
6:0 VCO_CALFREQ_RX: VCO Cbank frequency calibration word to be used in RX.

Definition at line 1290 of file S2LP_Regs.h.

◆ VCO_CALIBR_IN1_ADDR

#define VCO_CALIBR_IN1_ADDR ((uint8_t)0x6A)

Read and Write
Default value: 0x40
7 RESERVED: -
6:0 VCO_CALFREQ_TX: VCO Cbank frequency calibration word to be used in TX.

Definition at line 1276 of file S2LP_Regs.h.

◆ VCO_CALIBR_IN2_ADDR

#define VCO_CALIBR_IN2_ADDR ((uint8_t)0x69)

Read and Write
Default value: 0x88
7:4 VCO_CALAMP_TX: VCO magnitude calibration word (binary coding to be internally converted in thermometric code) used in TX.
3:0 VCO_CALAMP_RX: VCO magnitude calibration word (binary coding to be internally converted in thermometric code) used in RX.

Definition at line 1261 of file S2LP_Regs.h.

◆ VCO_CALIBR_OUT0_ADDR

#define VCO_CALIBR_OUT0_ADDR ((uint8_t)0x9A)

Read only
Default value: 0x00
7 RESERVED: -
6:0 VCO_CAL_FREQ_OUT: VCO Cbank frequency calibration output word (binary coding internally converted from thermometric coding).

Definition at line 1570 of file S2LP_Regs.h.

◆ VCO_CALIBR_OUT1_ADDR

#define VCO_CALIBR_OUT1_ADDR ((uint8_t)0x99)

Read only
Default value: 0x00
7:4 RESERVED: -
3:0 VCO_CAL_AMP_OUT: VCO magnitude calibration output word (binary coding internally converted from thermometric coding).

Definition at line 1556 of file S2LP_Regs.h.

◆ VCO_CONFIG_ADDR

#define VCO_CONFIG_ADDR ((uint8_t)0x68)

Read and Write
Default value: 0x02
6 RESERVED: -
VCO_CALAMP_EXT_SEL: 1 --> VCO amplitude calibration will be skipped (external amplitude word forced on VCO).
VCO_CALFREQ_EXT_SEL: 1 --> VCO frequency calibration will be skipped (external amplitude word forced on VCO).
RESERVED: -
0 RESERVED: -

Definition at line 1246 of file S2LP_Regs.h.

◆ XO_RCO_CONF0_ADDR

#define XO_RCO_CONF0_ADDR ((uint8_t)0x6D)

Read and Write
Default value: 0x30
EXT_REF: 0: reference signal from XO circuit, 1: reference signal from XIN pin.
4 GM_CONF: Set the driver gm of the XO at start up.
REFDIV: 1: enable the the reference clock divider.
RESERVED: -
EXT_RCO_OSC: 1: the 34.7 kHz signal must be supplied from any GPIO.
RCO_CALIBRATION: 1: enable the automatic RCO calibration.

Definition at line 1325 of file S2LP_Regs.h.

◆ XO_RCO_CONF1_ADDR

#define XO_RCO_CONF1_ADDR ((uint8_t)0x6C)

Read and Write
Default value: 0x6C
6 RESERVED: -
RESERVED: -
PD_CLKDIV: 1: disable both dividers of digital clock (and reference clockfor the SMPS) and IF-ADC clock.
2 RESERVED: -
0 RESERVED: -

Definition at line 1307 of file S2LP_Regs.h.

Macros