S2LP_PacketHandler.c

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/* Includes ------------------------------------------------------------------*/
#include "S2LP_PacketHandler.h"
#include "MCU_Interface.h"
#include "S2LP_PktWMbus.h"


#define IS_DIRECT_TX(MODE)  (((MODE) == NORMAL_TX_MODE) || \
           ((MODE) == DIRECT_TX_FIFO_MODE) || \
                             ((MODE) == DIRECT_TX_GPIO_MODE)  || \
                             ((MODE) == PN9_TX_MODE))

#define IS_DIRECT_RX(MODE)  (((MODE) == NORMAL_RX_MODE) || \
                 ((MODE) == DIRECT_RX_FIFO_MODE) || \
                 ((MODE) == DIRECT_RX_GPIO_MODE))


#define IS_PKT_SEQ_NUMBER_RELOAD(SEQN)                (SEQN<=3)

uint8_t S2LPGetPacketFormat(void)
{
  uint8_t tmp;

  /* Reads the PCKTCTRL2 register value */
  g_xStatus = S2LPSpiReadRegisters(PCKTCTRL3_ADDR, 1, &tmp);

  tmp &= PCKT_FRMT_REGMASK;
  tmp >>= 6;
  
  /* wmbus or basic */
  if(tmp==0x00) {
    if(S2LPPktWMbusGetSubmode() != WMBUS_SUBMODE_NOT_CONFIGURED) {
      tmp = 4; // wmbus
    }
  }
  return tmp;
}


void S2LPSetPreambleLength(uint16_t cPreambleLength)
{
  uint8_t tmpBuffer[2];
  
  s_assert_param(IS_PREAMBLE_LEN(cPreambleLength));
  
  S2LPSpiReadRegisters(PCKTCTRL6_ADDR, 1, &tmpBuffer[0]);

  /* Set the preamble length */
  tmpBuffer[0] &= ~PREAMBLE_LEN_9_8_REGMASK;
  tmpBuffer[0] |= (cPreambleLength>>8) & PREAMBLE_LEN_9_8_REGMASK;
  tmpBuffer[1] = cPreambleLength & PREAMBLE_LEN_7_0_REGMASK;

  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL6_ADDR, 2, tmpBuffer);

}


uint16_t S2LPGetPreambleLength(void)
{
  uint8_t tmpBuffer[2];

  /* Reads the PCKTCTRL2 register value */
  g_xStatus = S2LPSpiReadRegisters(PCKTCTRL6_ADDR, 2, tmpBuffer);

  /* Rebuild and return value */
  return ( ((((uint16_t)tmpBuffer[0])&PREAMBLE_LEN_9_8_REGMASK)<<8) | (((uint16_t)tmpBuffer[1]) + 1));

}


void S2LPSetSyncLength(uint8_t cSyncLength)
{
  uint8_t tmp;

  s_assert_param(IS_SYNC_LEN(cSyncLength));
  
  S2LPSpiReadRegisters(PCKTCTRL6_ADDR, 1, &tmp);

  tmp &= ~SYNC_LEN_REGMASK;
  tmp |= (cSyncLength<<2);

  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL6_ADDR, 1, &tmp);

}


uint8_t S2LPGetSyncLength(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKTCTRL6_ADDR, 1, &tmp);
  return (((tmp & SYNC_LEN_REGMASK)>>2) );

}


void S2LPPacketHandlerWhitening(SFunctionalState xNewState)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xNewState));

  S2LPSpiReadRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  if(xNewState == S_ENABLE) {
    tmp |= WHIT_EN_REGMASK;
  }
  else {
    tmp &= ~WHIT_EN_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL1_ADDR, 1, &tmp);

}


void S2LPPacketHandlerFec(SFunctionalState xNewState)
{
  uint8_t tmp;
  
  S2LPSpiReadRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  if(xNewState == S_ENABLE) {
    tmp |= FEC_EN_REGMASK;
  }
  else {
    tmp &= ~FEC_EN_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL1_ADDR, 1, &tmp);

}


void S2LPPacketHandlerManchester(SFunctionalState xNewState)
{
  uint8_t tmp;
  
  S2LPSpiReadRegisters(PCKTCTRL2_ADDR, 1, &tmp);

  tmp &= ~MANCHESTER_EN_REGMASK;
  tmp |= (((uint8_t)xNewState)<<1);

  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL2_ADDR, 1, &tmp);

}


void S2LPPacketHandler3OutOf6(SFunctionalState xNewState)
{
  uint8_t tmp;
  
  S2LPSpiReadRegisters(PCKTCTRL2_ADDR, 1, &tmp);

  tmp &= ~MBUS_3OF6_EN_REGMASK;
  tmp |= (((uint8_t)xNewState)<<2);

  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL2_ADDR, 1, &tmp);

}


void S2LPSetSyncWords(uint32_t lSyncWords, uint8_t cSyncLength)
{
  uint8_t tmpBuffer[4], tmp;
  
  /* Split the 32-bit value in 4 8-bit values */
  for(uint8_t i=0 ; i<4 ; i++) {
    tmpBuffer[i]=(uint8_t)(lSyncWords>>(8*i));
  }
  
  S2LPSpiReadRegisters(PCKTCTRL6_ADDR, 1, &tmp);
  
  tmp &= ~SYNC_LEN_REGMASK;
  tmp |= (cSyncLength<<2);
          
  S2LPSpiWriteRegisters(PCKTCTRL6_ADDR, 1, &tmp);
  
  /* Writes the new value on the PCKTCTRL2 register */
  g_xStatus = S2LPSpiWriteRegisters(SYNC3_ADDR, 4, tmpBuffer);

}


void S2LPGetSyncWords(uint32_t* lSyncWords, uint8_t* cSyncLength)
{
  uint8_t tmpBuffer[4], tmp;

  /* Reads the PCKTCTRL2 register value */
  S2LPSpiReadRegisters(PCKTCTRL6_ADDR, 1, &tmp);

  tmp &= SYNC_LEN_REGMASK;
  tmp >>= 2;
  *cSyncLength = tmp;
  
  g_xStatus = S2LPSpiReadRegisters(SYNC3_ADDR, 4, tmpBuffer);
  *lSyncWords = ((uint32_t)tmpBuffer[0]<<24) | ((uint32_t)tmpBuffer[1]<<16) | ((uint32_t)tmpBuffer[2]<<8) | ((uint32_t)tmpBuffer[3]);

}


void S2LPPktCommonFilterOnCrc(SFunctionalState xNewState)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xNewState));

  S2LPSpiReadRegisters(PCKT_FLT_OPTIONS_ADDR, 1, &tmp);
  if(xNewState == S_ENABLE) {
    tmp |= CRC_FLT_REGMASK;
  }
  else {
    tmp &= ~CRC_FLT_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_OPTIONS_ADDR, 1, &tmp);

}



uint8_t S2LPGetReceivedDestinationAddress(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(RX_ADDRE_FIELD0_ADDR, 1, &tmp);
  return tmp;
}


uint8_t S2LPGetReceivedSourceAddress(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(RX_ADDRE_FIELD1_ADDR, 1, &tmp);
  return tmp;
}


uint8_t S2LPGetMyAddress(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKT_FLT_GOALS0_ADDR, 1, &tmp);
  return tmp;
}


uint8_t S2LPGetBroadcastAddress(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKT_FLT_GOALS2_ADDR, 1, &tmp);
  return tmp;
}


uint8_t S2LPGetMulticastAddress(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKT_FLT_GOALS1_ADDR, 1, &tmp);
  return tmp;
}


uint8_t S2LPGetRxSourceMask(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKT_FLT_GOALS4_ADDR, 1, &tmp);
  return tmp;
}


uint8_t S2LPGetRxSourceReferenceAddress(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKT_FLT_GOALS3_ADDR, 1, &tmp);
  return tmp;
}



void S2LPSetRxSourceMask(uint8_t mask)
{
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_GOALS4_ADDR, 1, &mask);
}


void S2LPSetRxSourceReferenceAddress(uint8_t address)
{
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_GOALS3_ADDR, 1, &address);
}


void S2LPSetBroadcastAddress(uint8_t address)
{
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_GOALS2_ADDR, 1, &address);
}


void S2LPSetMulticastAddress(uint8_t address)
{
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_GOALS1_ADDR, 1, &address);
}



void S2LPSetMyAddress(uint8_t address)
{
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_GOALS0_ADDR, 1, &address);
}




void S2LPPacketHandlerSetRxMode(DirectRx xDirectRx)
{
  uint8_t tmp;
  s_assert_param(IS_DIRECT_RX(xDirectRx));

  S2LPSpiReadRegisters(PCKTCTRL3_ADDR, 1, &tmp);
  tmp &= ~RX_MODE_REGMASK;
  tmp |= (uint8_t)xDirectRx;
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL3_ADDR, 1, &tmp);

}


DirectRx S2LPPacketHandlerGetRxMode(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKTCTRL3_ADDR, 1, &tmp);
  return (DirectRx)(tmp & RX_MODE_REGMASK);

}


void S2LPPacketHandlerSetTxMode(DirectTx xDirectTx)
{
  uint8_t tmp;
  s_assert_param(IS_DIRECT_TX(xDirectTx));

  S2LPSpiReadRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  tmp &= ~TXSOURCE_REGMASK;
  tmp |= (uint8_t)xDirectTx;
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL1_ADDR, 1, &tmp);
}


DirectTx S2LPPacketHandlerGetTxMode(void)
{
  uint8_t tmp;
  g_xStatus = S2LPSpiReadRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  return (DirectTx)(tmp & TXSOURCE_REGMASK);
}

uint8_t S2LPPacketHandlerGetTransmittedSeqNumber(void)
{
  uint8_t tempRegValue;

  /* Reads the TX_PCKT_INFO register value */
  g_xStatus = S2LPSpiReadRegisters(TX_PCKT_INFO_ADDR, 1, &tempRegValue);

  /* Obtains and returns the TX sequence number */
  return (tempRegValue >> 4) & 0x07;

}

void S2LPPacketHandlerSetExtendedLenField(SFunctionalState xExtendedLenField)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xExtendedLenField));

  S2LPSpiReadRegisters(PCKTCTRL4_ADDR, 1, &tmp);
  if(xExtendedLenField == S_ENABLE) {
    tmp |= LEN_WID_REGMASK;
  }
  else {
    tmp &= ~LEN_WID_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL4_ADDR, 1, &tmp);
}


void S2LPPacketHandlerSwap4FSKSymbol(SFunctionalState xSwapSymbol)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xSwapSymbol));

  S2LPSpiReadRegisters(PCKTCTRL3_ADDR, 1, &tmp);
  if(xSwapSymbol == S_ENABLE) {
    tmp |= FSK4_SYM_SWAP_REGMASK;
  }
  else {
    tmp &= ~FSK4_SYM_SWAP_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL3_ADDR, 1, &tmp);
}

void S2LPPacketHandlerSwapFifoEndianess(SFunctionalState xEnableSwap)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xEnableSwap));

  S2LPSpiReadRegisters(PCKTCTRL3_ADDR, 1, &tmp);
  if(xEnableSwap == S_ENABLE) {
    tmp |= BYTE_SWAP_REGMASK;
  }
  else {
    tmp &= ~BYTE_SWAP_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL3_ADDR, 1, &tmp);
}

void S2LPPacketHandlerSwapPreamblePattern(SFunctionalState xEnableSwap)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xEnableSwap));

  S2LPSpiReadRegisters(PCKTCTRL3_ADDR, 1, &tmp);
  tmp&=0xFC;
  
  if(xEnableSwap == S_DISABLE) {
    tmp |= 0x01; 
  }
  
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL3_ADDR, 1, &tmp);
}



void S2LPPacketHandlerSetVariableLength(SFunctionalState xVarLen)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xVarLen));

  S2LPSpiReadRegisters(PCKTCTRL2_ADDR, 1, &tmp);
  if(xVarLen == S_ENABLE) {
    tmp |= FIX_VAR_LEN_REGMASK;
  }
  else {
    tmp &= ~FIX_VAR_LEN_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL2_ADDR, 1, &tmp);
}


void S2LPPacketHandlerSetCrcMode(PktCrcMode xPktCrcMode)
{
  uint8_t tmp;
  s_assert_param(IS_PKT_CRC_MODE(xPktCrcMode));

  S2LPSpiReadRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  tmp &= ~CRC_MODE_REGMASK;
  tmp |= (uint8_t)xPktCrcMode;
  S2LPSpiWriteRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  
}


PktCrcMode S2LPPacketHandlerGetCrcMode(void)
{
  uint8_t tmp;  
  S2LPSpiReadRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  tmp &= ~CRC_MODE_REGMASK;  
  return (PktCrcMode)tmp;  
}



void S2LPPacketHandlerSelectSecondarySync(SFunctionalState xSecondarySync)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xSecondarySync));

  S2LPSpiReadRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  if(xSecondarySync == S_ENABLE) {
    tmp |= SECOND_SYNC_SEL_REGMASK;
  }
  else {
    tmp &= ~SECOND_SYNC_SEL_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKTCTRL1_ADDR, 1, &tmp);
  
}


void S2LPPacketHandlerSetAutoPcktFilter(SFunctionalState xNewState)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xNewState));

  S2LPSpiReadRegisters(PROTOCOL1_ADDR, 1, &tmp);
  if(xNewState == S_ENABLE) {
    tmp |= AUTO_PCKT_FLT_REGMASK;
  }
  else {
    tmp &= ~AUTO_PCKT_FLT_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PROTOCOL1_ADDR, 1, &tmp);
}



void S2LPPacketHandlerSetRxPersistentMode(SFunctionalState xNewState)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xNewState));

  S2LPSpiReadRegisters(PROTOCOL0_ADDR, 1, &tmp);
  if(xNewState == S_ENABLE) {
    tmp |= PERS_RX_REGMASK;
  }
  else {
    tmp &= ~PERS_RX_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PROTOCOL0_ADDR, 1, &tmp);
}


void S2LPPacketHandlerSetSrcAddrFlt(SFunctionalState xNewState)
{
  uint8_t tmp;
  s_assert_param(IS_SFUNCTIONAL_STATE(xNewState));

  S2LPSpiReadRegisters(PCKT_FLT_OPTIONS_ADDR, 1, &tmp);
  if(xNewState == S_ENABLE) {
    tmp |= SOURCE_ADDR_FLT_REGMASK;
  }
  else {
    tmp &= ~SOURCE_ADDR_FLT_REGMASK;
  }
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_OPTIONS_ADDR, 1, &tmp);
}



void S2LPSetDualSyncWords(uint32_t lSyncWords)
{
  uint8_t tmpBuffer[4];
  
  /* Split the 32-bit value in 4 8-bit values */
  for(uint8_t i=0 ; i<4 ; i++) {
    tmpBuffer[i]=(uint8_t)(lSyncWords>>(8*i));
  }
  
  g_xStatus = S2LPSpiWriteRegisters(PCKT_FLT_GOALS3_ADDR, 4, tmpBuffer);
}


void S2LPGetDualSyncWords(uint32_t* lSyncWords)
{
  uint8_t tmpBuffer[4];
  
  g_xStatus = S2LPSpiReadRegisters(PCKT_FLT_GOALS3_ADDR, 4, tmpBuffer);
  *lSyncWords = ((uint32_t)tmpBuffer[0]<<24) | ((uint32_t)tmpBuffer[1]<<16) | ((uint32_t)tmpBuffer[2]<<8) | ((uint32_t)tmpBuffer[3]);
}


/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/