Appiko
LSM6DS3.h
1 /*
2  * File: LSM6DS3.h
3  * Copyright (c) 2017, Electronut Labs All rights reserved.
4  * Copyright (c) 2018 Appiko
5  * Created on 26 February, 2019, 12:54 PM
6  * Author: Tejas Vasekar (https://github.com/tejas-tj)
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions are met:
11  *
12  * 1. Redistributions of source code must retain the above copyright notice,
13  * this list of conditions and the following disclaimer.
14  *
15  * 2. Redistributions in binary form must reproduce the above copyright notice,
16  * this list of conditions and the following disclaimer in the documentation
17  * and/or other materials provided with the distribution.
18  *
19  * 3. Neither the name of the copyright holder nor the names of its contributors
20  * may be used to endorse or promote products derived from this software without
21  * specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  * POSSIBILITY OF SUCH DAMAGE
34  */
35 
36 
37 #ifndef LSM6DS3_H
38 #define LSM6DS3_H
39 
49 #include <stdint.h>
50 #include <stdbool.h>
51 #include "app_error.h"
52 #include "boards.h"
53 
54 /*Pin Definitions*/
55 #define INT1 15
56 #define INT2 20
57 #define SA0 31
58 
59 /*Device Address*/
60 //#define LSM6DS3_ADDR 0x6BU // SA0 HIGH.
61 #define LSM6DS3_ADDR 0x6AU // SA0 LOW.
62 
63 /*Register Addresses*/
64 
65 #define FIFO_CTRL1 0x06
66 #define FIFO_CTRL2 0x07
67 #define FIFO_CTRL3 0x08
68 #define FIFO_CTRL4 0x09
69 #define FIFO_CTRL5 0x0A
70 
71 #define INT1_CTRL 0x0D
72 #define INT2_CTRL 0x0E
73 
74 #define WHO_AM_I 0x0F
75 
76 #define CTRL1_XL 0x10
77 #define CTRL2_G 0x11
78 #define CTRL3_C 0x12
79 #define CTRL4_C 0x13
80 #define CTRL5_C 0x14
81 #define CTRL6_C 0x15
82 #define CTRL7_G 0x16
83 #define CTRL8_XL 0x17
84 #define CTRL9_XL 0x18
85 #define CTRL10_C 0x19
86 
87 #define MASTER_CONFIG 0x1A
88 
89 #define STATUS_REG 0x1E
90 
91 #define OUT_TEMP_L 0x20
92 #define OUT_TEMP 0x21
93 #define OUTX_L_G 0x22
94 #define OUTX_H_G 0x23
95 #define OUTY_L_G 0x24
96 #define OUTY_H_G 0x25
97 #define OUTZ_L_G 0x26
98 #define OUTZ_H_G 0x27
99 
100 #define OUTX_L_XL 0x28
101 #define OUTX_H_XL 0x29
102 #define OUTY_L_XL 0x2A
103 #define OUTY_H_XL 0x2B
104 #define OUTZ_L_XL 0x2C
105 #define OUTZ_H_XL 0x2D
106 
107 #define FIFO_STATUS1 0x3A
108 #define FIFO_STATUS2 0x3B
109 #define FIFO_STATUS3 0x3C
110 #define FIFO_STATUS4 0x3D
111 #define FIFO_DATA_OUT_L 0x3E
112 #define FIFO_DATA_OUT_H 0x3F
113 
114 #define FUNC_SRC 0x53
115 #define TAP_CFG 0x58
116 #define TAP_THRS_6D 0X59
117 #define INT_DUR2 0X5A
118 #define WAKE_UP_THRS 0X5B
119 #define WAKE_UP_DUR 0x5C
120 #define FREE_FALL 0x5D
121 #define MD1_CFG 0x5E
122 #define MD2_CFG 0x5F
123 
124 /*******************************************************************************
125 * Register : FIFO_CTRL1
126 * Address : 0X06
127 * Bit Group Name: WTM_FIFO
128 * Permission : R/W
129 *******************************************************************************/
130 #define LSM6DS3_IMU_WTM_FIFO_CTRL1_MASK 0xFF
131 #define LSM6DS3_IMU_WTM_FIFO_CTRL1_POSITION 0
132 #define LSM6DS3_IMU_WTM_FIFO_CTRL2_MASK 0x0F
133 #define LSM6DS3_IMU_WTM_FIFO_CTRL2_POSITION 0
134 
135 /*******************************************************************************
136 * Register : FIFO_CTRL2
137 * Address : 0X07
138 * Bit Group Name: TIM_PEDO_FIFO_DRDY
139 * Permission : R/W
140 *******************************************************************************/
141 typedef enum {
142  LSM6DS3_IMU_TIM_PEDO_FIFO_DRDY_DISABLED = 0x00,
143  LSM6DS3_IMU_TIM_PEDO_FIFO_DRDY_ENABLED = 0x40,
144 } LSM6DS3_IMU_TIM_PEDO_FIFO_DRDY_t;
145 
146 /*******************************************************************************
147 * Register : FIFO_CTRL2
148 * Address : 0X07
149 * Bit Group Name: TIM_PEDO_FIFO_EN
150 * Permission : R/W
151 *******************************************************************************/
152 typedef enum {
153  LSM6DS3_IMU_TIM_PEDO_FIFO_EN_DISABLED = 0x00,
154  LSM6DS3_IMU_TIM_PEDO_FIFO_EN_ENABLED = 0x80,
155 } LSM6DS3_IMU_TIM_PEDO_FIFO_EN_t;
156 
157 /*******************************************************************************
158 * Register : FIFO_CTRL3
159 * Address : 0X08
160 * Bit Group Name: DEC_FIFO_XL
161 * Permission : R/W
162 *******************************************************************************/
163 typedef enum {
164  LSM6DS3_IMU_DEC_FIFO_XL_DATA_NOT_IN_FIFO = 0x00,
165  LSM6DS3_IMU_DEC_FIFO_XL_NO_DECIMATION = 0x01,
166  LSM6DS3_IMU_DEC_FIFO_XL_DECIMATION_BY_2 = 0x02,
167  LSM6DS3_IMU_DEC_FIFO_XL_DECIMATION_BY_3 = 0x03,
168  LSM6DS3_IMU_DEC_FIFO_XL_DECIMATION_BY_4 = 0x04,
169  LSM6DS3_IMU_DEC_FIFO_XL_DECIMATION_BY_8 = 0x05,
170  LSM6DS3_IMU_DEC_FIFO_XL_DECIMATION_BY_16 = 0x06,
171  LSM6DS3_IMU_DEC_FIFO_XL_DECIMATION_BY_32 = 0x07,
172 } LSM6DS3_IMU_DEC_FIFO_XL_t;
173 
174 /*******************************************************************************
175 * Register : FIFO_CTRL3
176 * Address : 0X08
177 * Bit Group Name: DEC_FIFO_G
178 * Permission : R/W
179 *******************************************************************************/
180 typedef enum {
181  LSM6DS3_IMU_DEC_FIFO_G_DATA_NOT_IN_FIFO = 0x00,
182  LSM6DS3_IMU_DEC_FIFO_G_NO_DECIMATION = 0x08,
183  LSM6DS3_IMU_DEC_FIFO_G_DECIMATION_BY_2 = 0x10,
184  LSM6DS3_IMU_DEC_FIFO_G_DECIMATION_BY_3 = 0x18,
185  LSM6DS3_IMU_DEC_FIFO_G_DECIMATION_BY_4 = 0x20,
186  LSM6DS3_IMU_DEC_FIFO_G_DECIMATION_BY_8 = 0x28,
187  LSM6DS3_IMU_DEC_FIFO_G_DECIMATION_BY_16 = 0x30,
188  LSM6DS3_IMU_DEC_FIFO_G_DECIMATION_BY_32 = 0x38,
189 } LSM6DS3_IMU_DEC_FIFO_G_t;
190 
191 /*******************************************************************************
192 * Register : FIFO_CTRL4
193 * Address : 0X09
194 * Bit Group Name: DEC_FIFO_SLV0
195 * Permission : R/W
196 *******************************************************************************/
197 typedef enum {
198  LSM6DS3_IMU_DEC_FIFO_SLV0_DATA_NOT_IN_FIFO = 0x00,
199  LSM6DS3_IMU_DEC_FIFO_SLV0_NO_DECIMATION = 0x01,
200  LSM6DS3_IMU_DEC_FIFO_SLV0_DECIMATION_BY_2 = 0x02,
201  LSM6DS3_IMU_DEC_FIFO_SLV0_DECIMATION_BY_3 = 0x03,
202  LSM6DS3_IMU_DEC_FIFO_SLV0_DECIMATION_BY_4 = 0x04,
203  LSM6DS3_IMU_DEC_FIFO_SLV0_DECIMATION_BY_8 = 0x05,
204  LSM6DS3_IMU_DEC_FIFO_SLV0_DECIMATION_BY_16 = 0x06,
205  LSM6DS3_IMU_DEC_FIFO_SLV0_DECIMATION_BY_32 = 0x07,
206 } LSM6DS3_IMU_DEC_FIFO_SLV0_t;
207 
208 /*******************************************************************************
209 * Register : FIFO_CTRL4
210 * Address : 0X09
211 * Bit Group Name: DEC_FIFO_SLV1
212 * Permission : R/W
213 *******************************************************************************/
214 typedef enum {
215  LSM6DS3_IMU_DEC_FIFO_SLV1_DATA_NOT_IN_FIFO = 0x00,
216  LSM6DS3_IMU_DEC_FIFO_SLV1_NO_DECIMATION = 0x08,
217  LSM6DS3_IMU_DEC_FIFO_SLV1_DECIMATION_BY_2 = 0x10,
218  LSM6DS3_IMU_DEC_FIFO_SLV1_DECIMATION_BY_3 = 0x18,
219  LSM6DS3_IMU_DEC_FIFO_SLV1_DECIMATION_BY_4 = 0x20,
220  LSM6DS3_IMU_DEC_FIFO_SLV1_DECIMATION_BY_8 = 0x28,
221  LSM6DS3_IMU_DEC_FIFO_SLV1_DECIMATION_BY_16 = 0x30,
222  LSM6DS3_IMU_DEC_FIFO_SLV1_DECIMATION_BY_32 = 0x38,
223 } LSM6DS3_IMU_DEC_FIFO_SLV1_t;
224 
225 /*******************************************************************************
226 * Register : FIFO_CTRL4
227 * Address : 0X09
228 * Bit Group Name: HI_DATA_ONLY
229 * Permission : R/W
230 *******************************************************************************/
231 typedef enum {
232  LSM6DS3_IMU_HI_DATA_ONLY_DISABLED = 0x00,
233  LSM6DS3_IMU_HI_DATA_ONLY_ENABLED = 0x40,
234 } LSM6DS3_IMU_HI_DATA_ONLY_t;
235 
236 /*******************************************************************************
237 * Register : FIFO_CTRL5
238 * Address : 0X0A
239 * Bit Group Name: FIFO_MODE
240 * Permission : R/W
241 *******************************************************************************/
242 typedef enum {
243  LSM6DS3_IMU_FIFO_MODE_BYPASS = 0x00,
244  LSM6DS3_IMU_FIFO_MODE_FIFO = 0x01,
245  LSM6DS3_IMU_FIFO_MODE_STF = 0x03,
246  LSM6DS3_IMU_FIFO_MODE_BTS = 0x04,
247  LSM6DS3_IMU_FIFO_MODE_STREAM = 0x06,
248 } LSM6DS3_IMU_FIFO_MODE_t;
249 
250 /*******************************************************************************
251 * Register : FIFO_CTRL5
252 * Address : 0X0A
253 * Bit Group Name: ODR_FIFO
254 * Permission : R/W
255 *******************************************************************************/
256 typedef enum {
257  LSM6DS3_IMU_ODR_FIFO_13Hz = 0x08,
258  LSM6DS3_IMU_ODR_FIFO_26Hz = 0x10,
259  LSM6DS3_IMU_ODR_FIFO_52Hz = 0x18,
260  LSM6DS3_IMU_ODR_FIFO_104Hz = 0x20,
261  LSM6DS3_IMU_ODR_FIFO_208Hz = 0x28,
262  LSM6DS3_IMU_ODR_FIFO_416Hz = 0x30,
263  LSM6DS3_IMU_ODR_FIFO_833Hz = 0x38,
264  LSM6DS3_IMU_ODR_FIFO_1660Hz = 0x40,
265  LSM6DS3_IMU_ODR_FIFO_3330Hz = 0x48,
266  LSM6DS3_IMU_ODR_FIFO_6660Hz = 0x50,
267 } LSM6DS3_IMU_ODR_FIFO_t;
268 
269 /*******************************************************************************
270 * Register : INT1_CTRL
271 * Address : 0X0D
272 * Bit Group Name: INT1_DRDY_XL
273 * Permission : R/W
274 *******************************************************************************/
275 typedef enum {
276  LSM6DS3_IMU_INT1_DRDY_XL_DISABLED = 0x00,
277  LSM6DS3_IMU_INT1_DRDY_XL_ENABLED = 0x01,
278 } LSM6DS3_IMU_INT1_DRDY_XL_t;
279 
280 /*******************************************************************************
281 * Register : INT1_CTRL
282 * Address : 0X0D
283 * Bit Group Name: INT1_DRDY_G
284 * Permission : RW
285 *******************************************************************************/
286 typedef enum {
287  LSM6DS3_IMU_INT1_DRDY_G_DISABLED = 0x00,
288  LSM6DS3_IMU_INT1_DRDY_G_ENABLED = 0x02,
289 } LSM6DS3_IMU_INT1_DRDY_G_t;
290 
291 /*******************************************************************************
292 * Register : INT1_CTRL
293 * Address : 0X0D
294 * Bit Group Name: INT1_BOOT
295 * Permission : RW
296 *******************************************************************************/
297 typedef enum {
298  LSM6DS3_IMU_INT1_BOOT_DISABLED = 0x00,
299  LSM6DS3_IMU_INT1_BOOT_ENABLED = 0x04,
300 } LSM6DS3_IMU_INT1_BOOT_t;
301 
302 /*******************************************************************************
303 * Register : INT1_CTRL
304 * Address : 0X0D
305 * Bit Group Name: INT1_FTH
306 * Permission : RW
307 *******************************************************************************/
308 typedef enum {
309  LSM6DS3_IMU_INT1_FTH_DISABLED = 0x00,
310  LSM6DS3_IMU_INT1_FTH_ENABLED = 0x08,
311 } LSM6DS3_IMU_INT1_FTH_t;
312 
313 /*******************************************************************************
314 * Register : INT1_CTRL
315 * Address : 0X0D
316 * Bit Group Name: INT1_OVR
317 * Permission : RW
318 *******************************************************************************/
319 typedef enum {
320  LSM6DS3_IMU_INT1_OVR_DISABLED = 0x00,
321  LSM6DS3_IMU_INT1_OVR_ENABLED = 0x10,
322 } LSM6DS3_IMU_INT1_OVR_t;
323 
324 /*******************************************************************************
325 * Register : INT1_CTRL
326 * Address : 0X0D
327 * Bit Group Name: INT1_FSS5
328 * Permission : RW
329 *******************************************************************************/
330 typedef enum {
331  LSM6DS3_IMU_INT1_FSS5_DISABLED = 0x00,
332  LSM6DS3_IMU_INT1_FSS5_ENABLED = 0x20,
333 } LSM6DS3_IMU_INT1_FSS5_t;
334 
335 /*******************************************************************************
336 * Register : INT1_CTRL
337 * Address : 0X0D
338 * Bit Group Name: INT1_SIGN_MOT
339 * Permission : RW
340 *******************************************************************************/
341 typedef enum {
342  LSM6DS3_IMU_INT1_SIGN_MOT_DISABLED = 0x00,
343  LSM6DS3_IMU_INT1_SIGN_MOT_ENABLED = 0x40,
344 } LSM6DS3_IMU_INT1_SIGN_MOT_t;
345 
346 /*******************************************************************************
347 * Register : INT1_CTRL
348 * Address : 0X0D
349 * Bit Group Name: INT1_PEDO
350 * Permission : RW
351 *******************************************************************************/
352 typedef enum {
353  LSM6DS3_IMU_INT1_PEDO_DISABLED = 0x00,
354  LSM6DS3_IMU_INT1_PEDO_ENABLED = 0x80,
355 } LSM6DS3_IMU_INT1_PEDO_t;
356 
357 /*******************************************************************************
358 * Register : INT2_CTRL
359 * Address : 0X0E
360 * Bit Group Name: INT2_DRDY_XL
361 * Permission : RW
362 *******************************************************************************/
363 typedef enum {
364  LSM6DS3_IMU_INT2_DRDY_XL_DISABLED = 0x00,
365  LSM6DS3_IMU_INT2_DRDY_XL_ENABLED = 0x01,
366 } LSM6DS3_IMU_INT2_DRDY_XL_t;
367 
368 /*******************************************************************************
369 * Register : INT2_CTRL
370 * Address : 0X0E
371 * Bit Group Name: INT2_DRDY_G
372 * Permission : RW
373 *******************************************************************************/
374 typedef enum {
375  LSM6DS3_IMU_INT2_DRDY_G_DISABLED = 0x00,
376  LSM6DS3_IMU_INT2_DRDY_G_ENABLED = 0x02,
377 } LSM6DS3_IMU_INT2_DRDY_G_t;
378 
379 /*******************************************************************************
380 * Register : INT2_CTRL
381 * Address : 0X0E
382 * Bit Group Name: INT2_FTH
383 * Permission : RW
384 *******************************************************************************/
385 typedef enum {
386  LSM6DS3_IMU_INT2_FTH_DISABLED = 0x00,
387  LSM6DS3_IMU_INT2_FTH_ENABLED = 0x08,
388 } LSM6DS3_IMU_INT2_FTH_t;
389 
390 /*******************************************************************************
391 * Register : INT2_CTRL
392 * Address : 0X0E
393 * Bit Group Name: INT2_OVR
394 * Permission : RW
395 *******************************************************************************/
396 typedef enum {
397  LSM6DS3_IMU_INT2_OVR_DISABLED = 0x00,
398  LSM6DS3_IMU_INT2_OVR_ENABLED = 0x10,
399 } LSM6DS3_IMU_INT2_OVR_t;
400 
401 /*******************************************************************************
402 * Register : INT2_CTRL
403 * Address : 0X0E
404 * Bit Group Name: INT2_FSS5
405 * Permission : RW
406 *******************************************************************************/
407 typedef enum {
408  LSM6DS3_IMU_INT2_FSS5_DISABLED = 0x00,
409  LSM6DS3_IMU_INT2_FSS5_ENABLED = 0x20,
410 } LSM6DS3_IMU_INT2_FSS5_t;
411 
412 /*******************************************************************************
413 * Register : INT2_CTRL
414 * Address : 0X0E
415 * Bit Group Name: INT2_SIGN_MOT
416 * Permission : RW
417 *******************************************************************************/
418 typedef enum {
419  LSM6DS3_IMU_INT2_SIGN_MOT_DISABLED = 0x00,
420  LSM6DS3_IMU_INT2_SIGN_MOT_ENABLED = 0x40,
421 } LSM6DS3_IMU_INT2_SIGN_MOT_t;
422 
423 /*******************************************************************************
424 * Register : INT2_CTRL
425 * Address : 0X0E
426 * Bit Group Name: INT2_PEDO
427 * Permission : RW
428 *******************************************************************************/
429 typedef enum {
430  LSM6DS3_IMU_INT2_PEDO_DISABLED = 0x00,
431  LSM6DS3_IMU_INT2_PEDO_ENABLED = 0x80,
432 } LSM6DS3_IMU_INT2_PEDO_t;
433 
434 
435 /*******************************************************************************
436 * Register : CTRL1_XL
437 * Address : 0X10
438 * Bit Group Name: BW_XL
439 * Permission : R/W
440 *******************************************************************************/
441 typedef enum {
442  LSM6DS3_IMU_BW_XL_400Hz = 0x00,
443  LSM6DS3_IMU_BW_XL_200Hz = 0x01,
444  LSM6DS3_IMU_BW_XL_100Hz = 0x02,
445  LSM6DS3_IMU_BW_XL_50Hz = 0x03,
446 } LSM6DS3_IMU_BW_XL_t;
447 
448 /*******************************************************************************
449 * Register : CTRL1_XL
450 * Address : 0X10
451 * Bit Group Name: FS_XL
452 * Permission : R/W
453 *******************************************************************************/
454 typedef enum {
455  LSM6DS3_IMU_FS_XL_2g = 0x00,
456  LSM6DS3_IMU_FS_XL_16g = 0x04,
457  LSM6DS3_IMU_FS_XL_4g = 0x08,
458  LSM6DS3_IMU_FS_XL_8g = 0x0C,
459 } LSM6DS3_IMU_FS_XL_t;
460 
461 /*******************************************************************************
462 * Register : CTRL1_XL
463 * Address : 0X10
464 * Bit Group Name: ODR_XL
465 * Permission : R/W
466 *******************************************************************************/
467 typedef enum {
468  LSM6DS3_IMU_ODR_XL_POWER_DOWN = 0x00,
469  LSM6DS3_IMU_ODR_XL_13Hz = 0x10,
470  LSM6DS3_IMU_ODR_XL_26Hz = 0x20,
471  LSM6DS3_IMU_ODR_XL_52Hz = 0x30,
472  LSM6DS3_IMU_ODR_XL_104Hz = 0x40,
473  LSM6DS3_IMU_ODR_XL_208Hz = 0x50,
474  LSM6DS3_IMU_ODR_XL_416Hz = 0x60,
475  LSM6DS3_IMU_ODR_XL_833Hz = 0x70,
476  LSM6DS3_IMU_ODR_XL_1660Hz = 0x80,
477  LSM6DS3_IMU_ODR_XL_3330Hz = 0x90,
478  LSM6DS3_IMU_ODR_XL_6660Hz = 0xA0,
479 } LSM6DS3_IMU_ODR_XL_t;
480 
481 /*******************************************************************************
482 * Register : CTRL2_G
483 * Address : 0X11
484 * Bit Group Name: FS_125
485 * Permission : R/W
486 *******************************************************************************/
487 typedef enum {
488  LSM6DS3_IMU_FS_125_DISABLED = 0x00,
489  LSM6DS3_IMU_FS_125_ENABLED = 0x02,
490 } LSM6DS3_IMU_FS_125_t;
491 
492 /*******************************************************************************
493 * Register : CTRL2_G
494 * Address : 0X11
495 * Bit Group Name: FS_G
496 * Permission : R/W
497 *******************************************************************************/
498 typedef enum {
499  LSM6DS3_IMU_FS_G_245dps = 0x00,
500  LSM6DS3_IMU_FS_G_500dps = 0x04,
501  LSM6DS3_IMU_FS_G_1000dps = 0x08,
502  LSM6DS3_IMU_FS_G_2000dps = 0x0C,
503 } LSM6DS3_IMU_FS_G_t;
504 
505 /*******************************************************************************
506 * Register : CTRL2_G
507 * Address : 0X11
508 * Bit Group Name: ODR_G
509 * Permission : R/W
510 *******************************************************************************/
511 typedef enum {
512  LSM6DS3_IMU_ODR_G_POWER_DOWN = 0x00,
513  LSM6DS3_IMU_ODR_G_13Hz = 0x10,
514  LSM6DS3_IMU_ODR_G_26Hz = 0x20,
515  LSM6DS3_IMU_ODR_G_52Hz = 0x30,
516  LSM6DS3_IMU_ODR_G_104Hz = 0x40,
517  LSM6DS3_IMU_ODR_G_208Hz = 0x50,
518  LSM6DS3_IMU_ODR_G_416Hz = 0x60,
519  LSM6DS3_IMU_ODR_G_833Hz = 0x70,
520  LSM6DS3_IMU_ODR_G_1660Hz = 0x80,
521 } LSM6DS3_IMU_ODR_G_t;
522 
523 /*******************************************************************************
524 * Register : CTRL3_C
525 * Address : 0X12
526 * Bit Group Name: SW_RESET
527 * Permission : RW
528 *******************************************************************************/
529 typedef enum {
530  LSM6DS3_IMU_SW_RESET_NORMAL_MODE = 0x00,
531  LSM6DS3_IMU_SW_RESET_RESET_DEVICE = 0x01,
532 } LSM6DS3_IMU_SW_RESET_t;
533 
534 /*******************************************************************************
535 * Register : CTRL3_C
536 * Address : 0X12
537 * Bit Group Name: BLE
538 * Permission : RW
539 *******************************************************************************/
540 typedef enum {
541  LSM6DS3_IMU_BLE_LSB = 0x00,
542  LSM6DS3_IMU_BLE_MSB = 0x02,
543 } LSM6DS3_IMU_BLE_t;
544 
545 /*******************************************************************************
546 * Register : CTRL3_C
547 * Address : 0X12
548 * Bit Group Name: IF_INC
549 * Permission : RW
550 *******************************************************************************/
551 typedef enum {
552  LSM6DS3_IMU_IF_INC_DISABLED = 0x00,
553  LSM6DS3_IMU_IF_INC_ENABLED = 0x04,
554 } LSM6DS3_IMU_IF_INC_t;
555 
556 /*******************************************************************************
557 * Register : CTRL3_C
558 * Address : 0X12
559 * Bit Group Name: SIM
560 * Permission : RW
561 *******************************************************************************/
562 typedef enum {
563  LSM6DS3_IMU_SIM_4_WIRE = 0x00,
564  LSM6DS3_IMU_SIM_3_WIRE = 0x08,
565 } LSM6DS3_IMU_SIM_t;
566 
567 /*******************************************************************************
568 * Register : CTRL3_C
569 * Address : 0X12
570 * Bit Group Name: PP_OD
571 * Permission : RW
572 *******************************************************************************/
573 typedef enum {
574  LSM6DS3_IMU_PP_OD_PUSH_PULL = 0x00,
575  LSM6DS3_IMU_PP_OD_OPEN_DRAIN = 0x10,
576 } LSM6DS3_IMU_PP_OD_t;
577 
578 /*******************************************************************************
579 * Register : CTRL3_C
580 * Address : 0X12
581 * Bit Group Name: INT_ACT_LEVEL
582 * Permission : RW
583 *******************************************************************************/
584 typedef enum {
585  LSM6DS3_IMU_INT_ACT_LEVEL_ACTIVE_HI = 0x00,
586  LSM6DS3_IMU_INT_ACT_LEVEL_ACTIVE_LO = 0x20,
587 } LSM6DS3_IMU_INT_ACT_LEVEL_t;
588 
589 /*******************************************************************************
590 * Register : CTRL3_C
591 * Address : 0X12
592 * Bit Group Name: BDU
593 * Permission : RW
594 *******************************************************************************/
595 typedef enum {
596  LSM6DS3_IMU_BDU_CONTINUOS = 0x00,
597  LSM6DS3_IMU_BDU_BLOCK_UPDATE = 0x40,
598 } LSM6DS3_IMU_BDU_t;
599 
600 /*******************************************************************************
601 * Register : CTRL3_C
602 * Address : 0X12
603 * Bit Group Name: BOOT
604 * Permission : RW
605 *******************************************************************************/
606 typedef enum {
607  LSM6DS3_IMU_BOOT_NORMAL_MODE = 0x00,
608  LSM6DS3_IMU_BOOT_REBOOT_MODE = 0x80,
609 } LSM6DS3_IMU_BOOT_t;
610 
611 /*******************************************************************************
612 * Register : CTRL4_C
613 * Address : 0X13
614 * Bit Group Name: STOP_ON_FTH
615 * Permission : RW
616 *******************************************************************************/
617 typedef enum {
618  LSM6DS3_IMU_STOP_ON_FTH_DISABLED = 0x00,
619  LSM6DS3_IMU_STOP_ON_FTH_ENABLED = 0x01,
620 } LSM6DS3_IMU_STOP_ON_FTH_t;
621 
622 /*******************************************************************************
623 * Register : CTRL4_C
624 * Address : 0X13
625 * Bit Group Name: MODE3_EN
626 * Permission : RW
627 *******************************************************************************/
628 typedef enum {
629  LSM6DS3_IMU_MODE3_EN_DISABLED = 0x00,
630  LSM6DS3_IMU_MODE3_EN_ENABLED = 0x02,
631 } LSM6DS3_IMU_MODE3_EN_t;
632 
633 /*******************************************************************************
634 * Register : CTRL4_C
635 * Address : 0X13
636 * Bit Group Name: I2C_DISABLE
637 * Permission : RW
638 *******************************************************************************/
639 typedef enum {
640  LSM6DS3_IMU_I2C_DISABLE_I2C_AND_SPI = 0x00,
641  LSM6DS3_IMU_I2C_DISABLE_SPI_ONLY = 0x04,
642 } LSM6DS3_IMU_I2C_DISABLE_t;
643 
644 /*******************************************************************************
645 * Register : CTRL4_C
646 * Address : 0X13
647 * Bit Group Name: DRDY_MSK
648 * Permission : RW
649 *******************************************************************************/
650 typedef enum {
651  LSM6DS3_IMU_DRDY_MSK_DISABLED = 0x00,
652  LSM6DS3_IMU_DRDY_MSK_ENABLED = 0x08,
653 } LSM6DS3_IMU_DRDY_MSK_t;
654 
655 /*******************************************************************************
656 * Register : CTRL4_C
657 * Address : 0X13
658 * Bit Group Name: FIFO_TEMP_EN
659 * Permission : RW
660 *******************************************************************************/
661 typedef enum {
662  LSM6DS3_IMU_FIFO_TEMP_EN_DISABLED = 0x00,
663  LSM6DS3_IMU_FIFO_TEMP_EN_ENABLED = 0x10,
664 } LSM6DS3_IMU_FIFO_TEMP_EN_t;
665 
666 /*******************************************************************************
667 * Register : CTRL4_C
668 * Address : 0X13
669 * Bit Group Name: INT2_ON_INT1
670 * Permission : RW
671 *******************************************************************************/
672 typedef enum {
673  LSM6DS3_IMU_INT2_ON_INT1_DISABLED = 0x00,
674  LSM6DS3_IMU_INT2_ON_INT1_ENABLED = 0x20,
675 } LSM6DS3_IMU_INT2_ON_INT1_t;
676 
677 /*******************************************************************************
678 * Register : CTRL4_C
679 * Address : 0X13
680 * Bit Group Name: SLEEP_G
681 * Permission : RW
682 *******************************************************************************/
683 typedef enum {
684  LSM6DS3_IMU_SLEEP_G_DISABLED = 0x00,
685  LSM6DS3_IMU_SLEEP_G_ENABLED = 0x40,
686 } LSM6DS3_IMU_SLEEP_G_t;
687 
688 /*******************************************************************************
689 * Register : CTRL4_C
690 * Address : 0X13
691 * Bit Group Name: BW_SCAL_ODR
692 * Permission : RW
693 *******************************************************************************/
694 typedef enum {
695  LSM6DS3_IMU_BW_SCAL_ODR_DISABLED = 0x00,
696  LSM6DS3_IMU_BW_SCAL_ODR_ENABLED = 0x80,
697 } LSM6DS3_IMU_BW_SCAL_ODR_t;
698 
699 /*******************************************************************************
700 * Register : CTRL5_C
701 * Address : 0X14
702 * Bit Group Name: ST_XL
703 * Permission : RW
704 *******************************************************************************/
705 typedef enum {
706  LSM6DS3_IMU_ST_XL_NORMAL_MODE = 0x00,
707  LSM6DS3_IMU_ST_XL_POS_SIGN_TEST = 0x01,
708  LSM6DS3_IMU_ST_XL_NEG_SIGN_TEST = 0x02,
709  LSM6DS3_IMU_ST_XL_NA = 0x03,
710 } LSM6DS3_IMU_ST_XL_t;
711 
712 /*******************************************************************************
713 * Register : CTRL5_C
714 * Address : 0X14
715 * Bit Group Name: ST_G
716 * Permission : RW
717 *******************************************************************************/
718 typedef enum {
719  LSM6DS3_IMU_ST_G_NORMAL_MODE = 0x00,
720  LSM6DS3_IMU_ST_G_POS_SIGN_TEST = 0x04,
721  LSM6DS3_IMU_ST_G_NA = 0x08,
722  LSM6DS3_IMU_ST_G_NEG_SIGN_TEST = 0x0C,
723 } LSM6DS3_IMU_ST_G_t;
724 
725 /*******************************************************************************
726 * Register : CTRL6_G
727 * Address : 0X15
728 * Bit Group Name: LP_XL
729 * Permission : RW
730 *******************************************************************************/
731 typedef enum {
732  LSM6DS3_IMU_LP_XL_DISABLED = 0x00,
733  LSM6DS3_IMU_LP_XL_ENABLED = 0x10,
734 } LSM6DS3_IMU_LP_XL_t;
735 
736 /*******************************************************************************
737 * Register : CTRL6_G
738 * Address : 0X15
739 * Bit Group Name: DEN_LVL2_EN
740 * Permission : RW
741 *******************************************************************************/
742 typedef enum {
743  LSM6DS3_IMU_DEN_LVL2_EN_DISABLED = 0x00,
744  LSM6DS3_IMU_DEN_LVL2_EN_ENABLED = 0x20,
745 } LSM6DS3_IMU_DEN_LVL2_EN_t;
746 
747 /*******************************************************************************
748 * Register : CTRL6_G
749 * Address : 0X15
750 * Bit Group Name: DEN_LVL_EN
751 * Permission : RW
752 *******************************************************************************/
753 typedef enum {
754  LSM6DS3_IMU_DEN_LVL_EN_DISABLED = 0x00,
755  LSM6DS3_IMU_DEN_LVL_EN_ENABLED = 0x40,
756 } LSM6DS3_IMU_DEN_LVL_EN_t;
757 
758 /*******************************************************************************
759 * Register : CTRL6_G
760 * Address : 0X15
761 * Bit Group Name: DEN_EDGE_EN
762 * Permission : RW
763 *******************************************************************************/
764 typedef enum {
765  LSM6DS3_IMU_DEN_EDGE_EN_DISABLED = 0x00,
766  LSM6DS3_IMU_DEN_EDGE_EN_ENABLED = 0x80,
767 } LSM6DS3_IMU_DEN_EDGE_EN_t;
768 
769 /*******************************************************************************
770 * Register : CTRL7_G
771 * Address : 0X16
772 * Bit Group Name: HPM_G
773 * Permission : RW
774 *******************************************************************************/
775 typedef enum {
776  LSM6DS3_IMU_HPM_G_NORMAL_MODE = 0x00,
777  LSM6DS3_IMU_HPM_G_REF_SIGNAL = 0x10,
778  LSM6DS3_IMU_HPM_G_NORMAL_MODE_2 = 0x20,
779  LSM6DS3_IMU_HPM_G_AUTO_RESET_ON_INT = 0x30,
780 } LSM6DS3_IMU_HPM_G_t;
781 
782 /*******************************************************************************
783 * Register : CTRL7_G
784 * Address : 0X16
785 * Bit Group Name: HP_EN
786 * Permission : RW
787 *******************************************************************************/
788 typedef enum {
789  LSM6DS3_IMU_HP_EN_DISABLED = 0x00,
790  LSM6DS3_IMU_HP_EN_ENABLED = 0x40,
791 } LSM6DS3_IMU_HP_EN_t;
792 
793 /*******************************************************************************
794 * Register : CTRL7_G
795 * Address : 0X16
796 * Bit Group Name: LP_EN
797 * Permission : RW
798 *******************************************************************************/
799 typedef enum {
800  LSM6DS3_IMU_LP_EN_DISABLED = 0x00,
801  LSM6DS3_IMU_LP_EN_ENABLED = 0x80,
802 } LSM6DS3_IMU_LP_EN_t;
803 
804 /*******************************************************************************
805 * Register : CTRL8_XL
806 * Address : 0X17
807 * Bit Group Name: FDS
808 * Permission : RW
809 *******************************************************************************/
810 typedef enum {
811  LSM6DS3_IMU_FDS_FILTER_OFF = 0x00,
812  LSM6DS3_IMU_FDS_FILTER_ON = 0x04,
813 } LSM6DS3_IMU_FDS_t;
814 
815 /*******************************************************************************
816 * Register : CTRL9_XL
817 * Address : 0X18
818 * Bit Group Name: XEN_XL
819 * Permission : R/W
820 *******************************************************************************/
821 typedef enum {
822  LSM6DS3_IMU_XEN_XL_DISABLED = 0x00,
823  LSM6DS3_IMU_XEN_XL_ENABLED = 0x08,
824 } LSM6DS3_IMU_XEN_XL_t;
825 
826 /*******************************************************************************
827 * Register : CTRL9_XL
828 * Address : 0X18
829 * Bit Group Name: YEN_XL
830 * Permission : R/W
831 *******************************************************************************/
832 typedef enum {
833  LSM6DS3_IMU_YEN_XL_DISABLED = 0x00,
834  LSM6DS3_IMU_YEN_XL_ENABLED = 0x10,
835 } LSM6DS3_IMU_YEN_XL_t;
836 
837 /*******************************************************************************
838 * Register : CTRL9_XL
839 * Address : 0X18
840 * Bit Group Name: ZEN_XL
841 * Permission : R/W
842 *******************************************************************************/
843 typedef enum {
844  LSM6DS3_IMU_ZEN_XL_DISABLED = 0x00,
845  LSM6DS3_IMU_ZEN_XL_ENABLED = 0x20,
846 } LSM6DS3_IMU_ZEN_XL_t;
847 
848 /*******************************************************************************
849 * Register : CTRL10_C
850 * Address : 0X19
851 * Bit Group Name: SIGN_MOTION_EN
852 * Permission : R/W
853 *******************************************************************************/
854 typedef enum {
855  LSM6DS3_IMU_SIGN_MOTION_EN_DISABLED = 0x00,
856  LSM6DS3_IMU_SIGN_MOTION_EN_ENABLED = 0x01,
857 } LSM6DS3_IMU_SIGN_MOTION_EN_t;
858 
859 /*******************************************************************************
860 * Register : CTRL10_C
861 * Address : 0X19
862 * Bit Group Name: PEDO_RST_STEP
863 * Permission : R/W
864 *******************************************************************************/
865 typedef enum {
866  LSM6DS3_IMU_PEDO_RST_STEP_DISABLED = 0x00,
867  LSM6DS3_IMU_PEDO_RST_STEP_ENABLED = 0x02,
868 } LSM6DS3_IMU_PEDO_RST_STEP_t;
869 
870 /*******************************************************************************
871 * Register : CTRL10_C
872 * Address : 0X19
873 * Bit Group Name: XEN_G
874 * Permission : R/W
875 *******************************************************************************/
876 typedef enum {
877  LSM6DS3_IMU_XEN_G_DISABLED = 0x00,
878  LSM6DS3_IMU_XEN_G_ENABLED = 0x08,
879 } LSM6DS3_IMU_XEN_G_t;
880 
881 /*******************************************************************************
882 * Register : CTRL10_C
883 * Address : 0X19
884 * Bit Group Name: YEN_G
885 * Permission : R/W
886 *******************************************************************************/
887 typedef enum {
888  LSM6DS3_IMU_YEN_G_DISABLED = 0x00,
889  LSM6DS3_IMU_YEN_G_ENABLED = 0x10,
890 } LSM6DS3_IMU_YEN_G_t;
891 
892 /*******************************************************************************
893 * Register : CTRL10_C
894 * Address : 0X19
895 * Bit Group Name: ZEN_G
896 * Permission : R/W
897 *******************************************************************************/
898 typedef enum {
899  LSM6DS3_IMU_ZEN_G_DISABLED = 0x00,
900  LSM6DS3_IMU_ZEN_G_ENABLED = 0x20,
901 } LSM6DS3_IMU_ZEN_G_t;
902 
903 /*******************************************************************************
904 * Register : CTRL10_C
905 * Address : 0X19
906 * Bit Group Name: FUNC_EN
907 * Permission : R/W
908 *******************************************************************************/
909 typedef enum {
910  LSM6DS3_IMU_FUNC_EN_DISABLED = 0x00,
911  LSM6DS3_IMU_FUNC_EN_ENABLED = 0x04,
912 } LSM6DS3_IMU_FUNC_EN_t;
913 
914 
915 /*******************************************************************************
916 * Register : MASTER_CONFIG
917 * Address : 0X1A
918 * Bit Group Name: MASTER_ON
919 * Permission : RW
920 *******************************************************************************/
921 typedef enum {
922  LSM6DS3_IMU_MASTER_ON_DISABLED = 0x00,
923  LSM6DS3_IMU_MASTER_ON_ENABLED = 0x01,
924 } LSM6DS3_IMU_MASTER_ON_t;
925 
926 /*******************************************************************************
927 * Register : MASTER_CONFIG
928 * Address : 0X1A
929 * Bit Group Name: IRON_EN
930 * Permission : RW
931 *******************************************************************************/
932 typedef enum {
933  LSM6DS3_IMU_IRON_EN_DISABLED = 0x00,
934  LSM6DS3_IMU_IRON_EN_ENABLED = 0x02,
935 } LSM6DS3_IMU_IRON_EN_t;
936 
937 /*******************************************************************************
938 * Register : MASTER_CONFIG
939 * Address : 0X1A
940 * Bit Group Name: PASS_THRU_MODE
941 * Permission : RW
942 *******************************************************************************/
943 typedef enum {
944  LSM6DS3_IMU_PASS_THRU_MODE_DISABLED = 0x00,
945  LSM6DS3_IMU_PASS_THRU_MODE_ENABLED = 0x04,
946 } LSM6DS3_IMU_PASS_THRU_MODE_t;
947 
948 /*******************************************************************************
949 * Register : MASTER_CONFIG
950 * Address : 0X1A
951 * Bit Group Name: PULL_UP_EN
952 * Permission : RW
953 *******************************************************************************/
954 typedef enum {
955  LSM6DS3_IMU_PULL_UP_EN_DISABLED = 0x00,
956  LSM6DS3_IMU_PULL_UP_EN_ENABLED = 0x08,
957 } LSM6DS3_IMU_PULL_UP_EN_t;
958 
959 /*******************************************************************************
960 * Register : MASTER_CONFIG
961 * Address : 0X1A
962 * Bit Group Name: START_CONFIG
963 * Permission : RW
964 *******************************************************************************/
965 typedef enum {
966  LSM6DS3_IMU_START_CONFIG_XL_G_DRDY = 0x00,
967  LSM6DS3_IMU_START_CONFIG_EXT_INT2 = 0x10,
968 } LSM6DS3_IMU_START_CONFIG_t;
969 
970 /*******************************************************************************
971 * Register : MASTER_CONFIG
972 * Address : 0X1A
973 * Bit Group Name: DATA_VAL_SEL_FIFO
974 * Permission : RW
975 *******************************************************************************/
976 typedef enum {
977  LSM6DS3_IMU_DATA_VAL_SEL_FIFO_XL_G_DRDY = 0x00,
978  LSM6DS3_IMU_DATA_VAL_SEL_FIFO_SHUB_DRDY = 0x40,
979 } LSM6DS3_IMU_DATA_VAL_SEL_FIFO_t;
980 
981 /*******************************************************************************
982 * Register : MASTER_CONFIG
983 * Address : 0X1A
984 * Bit Group Name: DRDY_ON_INT1
985 * Permission : RW
986 *******************************************************************************/
987 typedef enum {
988  LSM6DS3_IMU_DRDY_ON_INT1_DISABLED = 0x00,
989  LSM6DS3_IMU_DRDY_ON_INT1_ENABLED = 0x80,
990 } LSM6DS3_IMU_DRDY_ON_INT1_t;
991 
992 /*******************************************************************************
993 * Register : WAKE_UP_SRC
994 * Address : 0X1B
995 * Bit Group Name: Z_WU
996 * Permission : RO
997 *******************************************************************************/
998 typedef enum {
999  LSM6DS3_IMU_Z_WU_NOT_DETECTED = 0x00,
1000  LSM6DS3_IMU_Z_WU_DETECTED = 0x01,
1001 } LSM6DS3_IMU_Z_WU_t;
1002 
1003 /*******************************************************************************
1004 * Register : WAKE_UP_SRC
1005 * Address : 0X1B
1006 * Bit Group Name: Y_WU
1007 * Permission : RO
1008 *******************************************************************************/
1009 typedef enum {
1010  LSM6DS3_IMU_Y_WU_NOT_DETECTED = 0x00,
1011  LSM6DS3_IMU_Y_WU_DETECTED = 0x02,
1012 } LSM6DS3_IMU_Y_WU_t;
1013 
1014 /*******************************************************************************
1015 * Register : WAKE_UP_SRC
1016 * Address : 0X1B
1017 * Bit Group Name: X_WU
1018 * Permission : RO
1019 *******************************************************************************/
1020 typedef enum {
1021  LSM6DS3_IMU_X_WU_NOT_DETECTED = 0x00,
1022  LSM6DS3_IMU_X_WU_DETECTED = 0x04,
1023 } LSM6DS3_IMU_X_WU_t;
1024 
1025 /*******************************************************************************
1026 * Register : WAKE_UP_SRC
1027 * Address : 0X1B
1028 * Bit Group Name: WU_EV_STATUS
1029 * Permission : RO
1030 *******************************************************************************/
1031 typedef enum {
1032  LSM6DS3_IMU_WU_EV_STATUS_NOT_DETECTED = 0x00,
1033  LSM6DS3_IMU_WU_EV_STATUS_DETECTED = 0x08,
1034 } LSM6DS3_IMU_WU_EV_STATUS_t;
1035 
1036 /*******************************************************************************
1037 * Register : WAKE_UP_SRC
1038 * Address : 0X1B
1039 * Bit Group Name: SLEEP_EV_STATUS
1040 * Permission : RO
1041 *******************************************************************************/
1042 typedef enum {
1043  LSM6DS3_IMU_SLEEP_EV_STATUS_NOT_DETECTED = 0x00,
1044  LSM6DS3_IMU_SLEEP_EV_STATUS_DETECTED = 0x10,
1045 } LSM6DS3_IMU_SLEEP_EV_STATUS_t;
1046 
1047 /*******************************************************************************
1048 * Register : WAKE_UP_SRC
1049 * Address : 0X1B
1050 * Bit Group Name: FF_EV_STATUS
1051 * Permission : RO
1052 *******************************************************************************/
1053 typedef enum {
1054  LSM6DS3_IMU_FF_EV_STATUS_NOT_DETECTED = 0x00,
1055  LSM6DS3_IMU_FF_EV_STATUS_DETECTED = 0x20,
1056 } LSM6DS3_IMU_FF_EV_STATUS_t;
1057 
1058 /*******************************************************************************
1059 * Register : TAP_SRC
1060 * Address : 0X1C
1061 * Bit Group Name: Z_TAP
1062 * Permission : RO
1063 *******************************************************************************/
1064 typedef enum {
1065  LSM6DS3_IMU_Z_TAP_NOT_DETECTED = 0x00,
1066  LSM6DS3_IMU_Z_TAP_DETECTED = 0x01,
1067 } LSM6DS3_IMU_Z_TAP_t;
1068 
1069 /*******************************************************************************
1070 * Register : TAP_SRC
1071 * Address : 0X1C
1072 * Bit Group Name: Y_TAP
1073 * Permission : RO
1074 *******************************************************************************/
1075 typedef enum {
1076  LSM6DS3_IMU_Y_TAP_NOT_DETECTED = 0x00,
1077  LSM6DS3_IMU_Y_TAP_DETECTED = 0x02,
1078 } LSM6DS3_IMU_Y_TAP_t;
1079 
1080 /*******************************************************************************
1081 * Register : TAP_SRC
1082 * Address : 0X1C
1083 * Bit Group Name: X_TAP
1084 * Permission : RO
1085 *******************************************************************************/
1086 typedef enum {
1087  LSM6DS3_IMU_X_TAP_NOT_DETECTED = 0x00,
1088  LSM6DS3_IMU_X_TAP_DETECTED = 0x04,
1089 } LSM6DS3_IMU_X_TAP_t;
1090 
1091 /*******************************************************************************
1092 * Register : TAP_SRC
1093 * Address : 0X1C
1094 * Bit Group Name: TAP_SIGN
1095 * Permission : RO
1096 *******************************************************************************/
1097 typedef enum {
1098  LSM6DS3_IMU_TAP_SIGN_POS_SIGN = 0x00,
1099  LSM6DS3_IMU_TAP_SIGN_NEG_SIGN = 0x08,
1100 } LSM6DS3_IMU_TAP_SIGN_t;
1101 
1102 /*******************************************************************************
1103 * Register : TAP_SRC
1104 * Address : 0X1C
1105 * Bit Group Name: DOUBLE_TAP_EV_STATUS
1106 * Permission : RO
1107 *******************************************************************************/
1108 typedef enum {
1109  LSM6DS3_IMU_DOUBLE_TAP_EV_STATUS_NOT_DETECTED = 0x00,
1110  LSM6DS3_IMU_DOUBLE_TAP_EV_STATUS_DETECTED = 0x10,
1111 } LSM6DS3_IMU_DOUBLE_TAP_EV_STATUS_t;
1112 
1113 /*******************************************************************************
1114 * Register : TAP_SRC
1115 * Address : 0X1C
1116 * Bit Group Name: SINGLE_TAP_EV_STATUS
1117 * Permission : RO
1118 *******************************************************************************/
1119 typedef enum {
1120  LSM6DS3_IMU_SINGLE_TAP_EV_STATUS_NOT_DETECTED = 0x00,
1121  LSM6DS3_IMU_SINGLE_TAP_EV_STATUS_DETECTED = 0x20,
1122 } LSM6DS3_IMU_SINGLE_TAP_EV_STATUS_t;
1123 
1124 /*******************************************************************************
1125 * Register : TAP_SRC
1126 * Address : 0X1C
1127 * Bit Group Name: TAP_EV_STATUS
1128 * Permission : RO
1129 *******************************************************************************/
1130 typedef enum {
1131  LSM6DS3_IMU_TAP_EV_STATUS_NOT_DETECTED = 0x00,
1132  LSM6DS3_IMU_TAP_EV_STATUS_DETECTED = 0x40,
1133 } LSM6DS3_IMU_TAP_EV_STATUS_t;
1134 
1135 /*******************************************************************************
1136 * Register : D6D_SRC
1137 * Address : 0X1D
1138 * Bit Group Name: DSD_XL
1139 * Permission : RO
1140 *******************************************************************************/
1141 typedef enum {
1142  LSM6DS3_IMU_DSD_XL_NOT_DETECTED = 0x00,
1143  LSM6DS3_IMU_DSD_XL_DETECTED = 0x01,
1144 } LSM6DS3_IMU_DSD_XL_t;
1145 
1146 /*******************************************************************************
1147 * Register : D6D_SRC
1148 * Address : 0X1D
1149 * Bit Group Name: DSD_XH
1150 * Permission : RO
1151 *******************************************************************************/
1152 typedef enum {
1153  LSM6DS3_IMU_DSD_XH_NOT_DETECTED = 0x00,
1154  LSM6DS3_IMU_DSD_XH_DETECTED = 0x02,
1155 } LSM6DS3_IMU_DSD_XH_t;
1156 
1157 /*******************************************************************************
1158 * Register : D6D_SRC
1159 * Address : 0X1D
1160 * Bit Group Name: DSD_YL
1161 * Permission : RO
1162 *******************************************************************************/
1163 typedef enum {
1164  LSM6DS3_IMU_DSD_YL_NOT_DETECTED = 0x00,
1165  LSM6DS3_IMU_DSD_YL_DETECTED = 0x04,
1166 } LSM6DS3_IMU_DSD_YL_t;
1167 
1168 /*******************************************************************************
1169 * Register : D6D_SRC
1170 * Address : 0X1D
1171 * Bit Group Name: DSD_YH
1172 * Permission : RO
1173 *******************************************************************************/
1174 typedef enum {
1175  LSM6DS3_IMU_DSD_YH_NOT_DETECTED = 0x00,
1176  LSM6DS3_IMU_DSD_YH_DETECTED = 0x08,
1177 } LSM6DS3_IMU_DSD_YH_t;
1178 
1179 /*******************************************************************************
1180 * Register : D6D_SRC
1181 * Address : 0X1D
1182 * Bit Group Name: DSD_ZL
1183 * Permission : RO
1184 *******************************************************************************/
1185 typedef enum {
1186  LSM6DS3_IMU_DSD_ZL_NOT_DETECTED = 0x00,
1187  LSM6DS3_IMU_DSD_ZL_DETECTED = 0x10,
1188 } LSM6DS3_IMU_DSD_ZL_t;
1189 
1190 /*******************************************************************************
1191 * Register : D6D_SRC
1192 * Address : 0X1D
1193 * Bit Group Name: DSD_ZH
1194 * Permission : RO
1195 *******************************************************************************/
1196 typedef enum {
1197  LSM6DS3_IMU_DSD_ZH_NOT_DETECTED = 0x00,
1198  LSM6DS3_IMU_DSD_ZH_DETECTED = 0x20,
1199 } LSM6DS3_IMU_DSD_ZH_t;
1200 
1201 /*******************************************************************************
1202 * Register : D6D_SRC
1203 * Address : 0X1D
1204 * Bit Group Name: D6D_EV_STATUS
1205 * Permission : RO
1206 *******************************************************************************/
1207 typedef enum {
1208  LSM6DS3_IMU_D6D_EV_STATUS_NOT_DETECTED = 0x00,
1209  LSM6DS3_IMU_D6D_EV_STATUS_DETECTED = 0x40,
1210 } LSM6DS3_IMU_D6D_EV_STATUS_t;
1211 
1212 /*******************************************************************************
1213 * Register : STATUS_REG
1214 * Address : 0X1E
1215 * Bit Group Name: XLDA
1216 * Permission : RO
1217 *******************************************************************************/
1218 typedef enum {
1219  LSM6DS3_IMU_XLDA_NO_DATA_AVAIL = 0x00,
1220  LSM6DS3_IMU_XLDA_DATA_AVAIL = 0x01,
1221 } LSM6DS3_IMU_XLDA_t;
1222 
1223 /*******************************************************************************
1224 * Register : STATUS_REG
1225 * Address : 0X1E
1226 * Bit Group Name: GDA
1227 * Permission : RO
1228 *******************************************************************************/
1229 typedef enum {
1230  LSM6DS3_IMU_GDA_NO_DATA_AVAIL = 0x00,
1231  LSM6DS3_IMU_GDA_DATA_AVAIL = 0x02,
1232 } LSM6DS3_IMU_GDA_t;
1233 
1234 /*******************************************************************************
1235 * Register : STATUS_REG
1236 * Address : 0X1E
1237 * Bit Group Name: EV_BOOT
1238 * Permission : RO
1239 *******************************************************************************/
1240 typedef enum {
1241  LSM6DS3_IMU_EV_BOOT_NO_BOOT_RUNNING = 0x00,
1242  LSM6DS3_IMU_EV_BOOT_BOOT_IS_RUNNING = 0x08,
1243 } LSM6DS3_IMU_EV_BOOT_t;
1244 
1245 /*******************************************************************************
1246 * Register : FIFO_STATUS1
1247 * Address : 0X3A
1248 * Bit Group Name: DIFF_FIFO
1249 * Permission : RO
1250 *******************************************************************************/
1251 #define LSM6DS3_IMU_DIFF_FIFO_STATUS1_MASK 0xFF
1252 #define LSM6DS3_IMU_DIFF_FIFO_STATUS1_POSITION 0
1253 #define LSM6DS3_IMU_DIFF_FIFO_STATUS2_MASK 0xF
1254 #define LSM6DS3_IMU_DIFF_FIFO_STATUS2_POSITION 0
1255 
1256 /*******************************************************************************
1257 * Register : FIFO_STATUS2
1258 * Address : 0X3B
1259 * Bit Group Name: FIFO_EMPTY
1260 * Permission : RO
1261 *******************************************************************************/
1262 typedef enum {
1263  LSM6DS3_IMU_FIFO_EMPTY_FIFO_NOT_EMPTY = 0x00,
1264  LSM6DS3_IMU_FIFO_EMPTY_FIFO_EMPTY = 0x10,
1265 } LSM6DS3_IMU_FIFO_EMPTY_t;
1266 
1267 /*******************************************************************************
1268 * Register : FIFO_STATUS2
1269 * Address : 0X3B
1270 * Bit Group Name: FIFO_FULL
1271 * Permission : RO
1272 *******************************************************************************/
1273 typedef enum {
1274  LSM6DS3_IMU_FIFO_FULL_FIFO_NOT_FULL = 0x00,
1275  LSM6DS3_IMU_FIFO_FULL_FIFO_FULL = 0x20,
1276 } LSM6DS3_IMU_FIFO_FULL_t;
1277 
1278 /*******************************************************************************
1279 * Register : FIFO_STATUS2
1280 * Address : 0X3B
1281 * Bit Group Name: OVERRUN
1282 * Permission : RO
1283 *******************************************************************************/
1284 typedef enum {
1285  LSM6DS3_IMU_OVERRUN_NO_OVERRUN = 0x00,
1286  LSM6DS3_IMU_OVERRUN_OVERRUN = 0x40,
1287 } LSM6DS3_IMU_OVERRUN_t;
1288 
1289 /*******************************************************************************
1290 * Register : FIFO_STATUS2
1291 * Address : 0X3B
1292 * Bit Group Name: WTM
1293 * Permission : RO
1294 *******************************************************************************/
1295 typedef enum {
1296  LSM6DS3_IMU_WTM_BELOW_WTM = 0x00,
1297  LSM6DS3_IMU_WTM_ABOVE_OR_EQUAL_WTM = 0x80,
1298 } LSM6DS3_IMU_WTM_t;
1299 
1300 /*******************************************************************************
1301 * Register : FIFO_STATUS3
1302 * Address : 0X3C
1303 * Bit Group Name: FIFO_PATTERN
1304 * Permission : RO
1305 *******************************************************************************/
1306 #define LSM6DS3_IMU_FIFO_STATUS3_PATTERN_MASK 0xFF
1307 #define LSM6DS3_IMU_FIFO_STATUS3_PATTERN_POSITION 0
1308 #define LSM6DS3_IMU_FIFO_STATUS4_PATTERN_MASK 0x03
1309 #define LSM6DS3_IMU_FIFO_STATUS4_PATTERN_POSITION 0
1310 
1311 /*******************************************************************************
1312 * Register : FUNC_SRC
1313 * Address : 0X53
1314 * Bit Group Name: SENS_HUB_END
1315 * Permission : RO
1316 *******************************************************************************/
1317 typedef enum {
1318  LSM6DS3_IMU_SENS_HUB_END_STILL_ONGOING = 0x00,
1319  LSM6DS3_IMU_SENS_HUB_END_OP_COMPLETED = 0x01,
1320 } LSM6DS3_IMU_SENS_HUB_END_t;
1321 
1322 /*******************************************************************************
1323 * Register : FUNC_SRC
1324 * Address : 0X53
1325 * Bit Group Name: SOFT_IRON_END
1326 * Permission : RO
1327 *******************************************************************************/
1328 typedef enum {
1329  LSM6DS3_IMU_SOFT_IRON_END_NOT_COMPLETED = 0x00,
1330  LSM6DS3_IMU_SOFT_IRON_END_COMPLETED = 0x02,
1331 } LSM6DS3_IMU_SOFT_IRON_END_t;
1332 
1333 /*******************************************************************************
1334 * Register : FUNC_SRC
1335 * Address : 0X53
1336 * Bit Group Name: PEDO_EV_STATUS
1337 * Permission : RO
1338 *******************************************************************************/
1339 typedef enum {
1340  LSM6DS3_IMU_PEDO_EV_STATUS_NOT_DETECTED = 0x00,
1341  LSM6DS3_IMU_PEDO_EV_STATUS_DETECTED = 0x10,
1342 } LSM6DS3_IMU_PEDO_EV_STATUS_t;
1343 
1344 /*******************************************************************************
1345 * Register : FUNC_SRC
1346 * Address : 0X53
1347 * Bit Group Name: TILT_EV_STATUS
1348 * Permission : RO
1349 *******************************************************************************/
1350 typedef enum {
1351  LSM6DS3_IMU_TILT_EV_STATUS_NOT_DETECTED = 0x00,
1352  LSM6DS3_IMU_TILT_EV_STATUS_DETECTED = 0x20,
1353 } LSM6DS3_IMU_TILT_EV_STATUS_t;
1354 
1355 /*******************************************************************************
1356 * Register : FUNC_SRC
1357 * Address : 0X53
1358 * Bit Group Name: SIGN_MOT_EV_STATUS
1359 * Permission : RO
1360 *******************************************************************************/
1361 typedef enum {
1362  LSM6DS3_IMU_SIGN_MOT_EV_STATUS_NOT_DETECTED = 0x00,
1363  LSM6DS3_IMU_SIGN_MOT_EV_STATUS_DETECTED = 0x40,
1364 } LSM6DS3_IMU_SIGN_MOT_EV_STATUS_t;
1365 
1366 /*******************************************************************************
1367 * Register : TAP_CFG
1368 * Address : 0X58
1369 * Bit Group Name: LIR
1370 * Permission : RW
1371 *******************************************************************************/
1372 typedef enum {
1373  LSM6DS3_IMU_LIR_DISABLED = 0x00,
1374  LSM6DS3_IMU_LIR_ENABLED = 0x01,
1375 } LSM6DS3_IMU_LIR_t;
1376 
1377 /*******************************************************************************
1378 * Register : TAP_CFG
1379 * Address : 0X58
1380 * Bit Group Name: TAP_Z_EN
1381 * Permission : RW
1382 *******************************************************************************/
1383 typedef enum {
1384  LSM6DS3_IMU_TAP_Z_EN_DISABLED = 0x00,
1385  LSM6DS3_IMU_TAP_Z_EN_ENABLED = 0x02,
1386 } LSM6DS3_IMU_TAP_Z_EN_t;
1387 
1388 /*******************************************************************************
1389 * Register : TAP_CFG
1390 * Address : 0X58
1391 * Bit Group Name: TAP_Y_EN
1392 * Permission : RW
1393 *******************************************************************************/
1394 typedef enum {
1395  LSM6DS3_IMU_TAP_Y_EN_DISABLED = 0x00,
1396  LSM6DS3_IMU_TAP_Y_EN_ENABLED = 0x04,
1397 } LSM6DS3_IMU_TAP_Y_EN_t;
1398 
1399 /*******************************************************************************
1400 * Register : TAP_CFG
1401 * Address : 0X58
1402 * Bit Group Name: TAP_X_EN
1403 * Permission : RW
1404 *******************************************************************************/
1405 typedef enum {
1406  LSM6DS3_IMU_TAP_X_EN_DISABLED = 0x00,
1407  LSM6DS3_IMU_TAP_X_EN_ENABLED = 0x08,
1408 } LSM6DS3_IMU_TAP_X_EN_t;
1409 
1410 /*******************************************************************************
1411 * Register : TAP_CFG
1412 * Address : 0X58
1413 * Bit Group Name: TILT_EN
1414 * Permission : RW
1415 *******************************************************************************/
1416 typedef enum {
1417  LSM6DS3_IMU_TILT_EN_DISABLED = 0x00,
1418  LSM6DS3_IMU_TILT_EN_ENABLED = 0x20,
1419 } LSM6DS3_IMU_TILT_EN_t;
1420 
1421 /*******************************************************************************
1422 * Register : TAP_CFG
1423 * Address : 0X58
1424 * Bit Group Name: PEDO_EN
1425 * Permission : RW
1426 *******************************************************************************/
1427 typedef enum {
1428  LSM6DS3_IMU_PEDO_EN_DISABLED = 0x00,
1429  LSM6DS3_IMU_PEDO_EN_ENABLED = 0x40,
1430 } LSM6DS3_IMU_PEDO_EN_t;
1431 
1432 /*******************************************************************************
1433 * Register : TAP_CFG
1434 * Address : 0X58
1435 * Bit Group Name: TIMER_EN
1436 * Permission : RW
1437 *******************************************************************************/
1438 typedef enum {
1439  LSM6DS3_IMU_TIMER_EN_DISABLED = 0x00,
1440  LSM6DS3_IMU_TIMER_EN_ENABLED = 0x80,
1441 } LSM6DS3_IMU_TIMER_EN_t;
1442 
1443 /*******************************************************************************
1444 * Register : TAP_THS_6D
1445 * Address : 0X59
1446 * Bit Group Name: TAP_THS
1447 * Permission : RW
1448 *******************************************************************************/
1449 #define LSM6DS3_IMU_TAP_THS_MASK 0x1F
1450 #define LSM6DS3_IMU_TAP_THS_POSITION 0
1451 
1452 /*******************************************************************************
1453 * Register : TAP_THS_6D
1454 * Address : 0X59
1455 * Bit Group Name: SIXD_THS
1456 * Permission : RW
1457 *******************************************************************************/
1458 typedef enum {
1459  LSM6DS3_IMU_SIXD_THS_80_degree = 0x00,
1460  LSM6DS3_IMU_SIXD_THS_70_degree = 0x20,
1461  LSM6DS3_IMU_SIXD_THS_60_degree = 0x40,
1462  LSM6DS3_IMU_SIXD_THS_50_degree = 0x60,
1463 } LSM6DS3_IMU_SIXD_THS_t;
1464 
1465 /*******************************************************************************
1466 * Register : INT_DUR2
1467 * Address : 0X5A
1468 * Bit Group Name: SHOCK
1469 * Permission : RW
1470 *******************************************************************************/
1471 #define LSM6DS3_IMU_SHOCK_MASK 0x03
1472 #define LSM6DS3_IMU_SHOCK_POSITION 0
1473 
1474 /*******************************************************************************
1475 * Register : INT_DUR2
1476 * Address : 0X5A
1477 * Bit Group Name: QUIET
1478 * Permission : RW
1479 *******************************************************************************/
1480 #define LSM6DS3_IMU_QUIET_MASK 0x0C
1481 #define LSM6DS3_IMU_QUIET_POSITION 2
1482 
1483 /*******************************************************************************
1484 * Register : INT_DUR2
1485 * Address : 0X5A
1486 * Bit Group Name: DUR
1487 * Permission : RW
1488 *******************************************************************************/
1489 #define LSM6DS3_IMU_DUR_MASK 0xF0
1490 #define LSM6DS3_IMU_DUR_POSITION 4
1491 
1492 /*******************************************************************************
1493 * Register : WAKE_UP_THS
1494 * Address : 0X5B
1495 * Bit Group Name: WK_THS
1496 * Permission : RW
1497 *******************************************************************************/
1498 #define LSM6DS3_IMU_WK_THS_MASK 0x3F
1499 #define LSM6DS3_IMU_WK_THS_POSITION 0
1500 
1501 /*******************************************************************************
1502 * Register : WAKE_UP_THS
1503 * Address : 0X5B
1504 * Bit Group Name: INACTIVITY_ON
1505 * Permission : RW
1506 *******************************************************************************/
1507 typedef enum {
1508  LSM6DS3_IMU_INACTIVITY_ON_DISABLED = 0x00,
1509  LSM6DS3_IMU_INACTIVITY_ON_ENABLED = 0x40,
1510 } LSM6DS3_IMU_INACTIVITY_ON_t;
1511 
1512 /*******************************************************************************
1513 * Register : WAKE_UP_THS
1514 * Address : 0X5B
1515 * Bit Group Name: SINGLE_DOUBLE_TAP
1516 * Permission : RW
1517 *******************************************************************************/
1518 typedef enum {
1519  LSM6DS3_IMU_SINGLE_DOUBLE_TAP_DOUBLE_TAP = 0x00,
1520  LSM6DS3_IMU_SINGLE_DOUBLE_TAP_SINGLE_TAP = 0x80,
1521 } LSM6DS3_IMU_SINGLE_DOUBLE_TAP_t;
1522 
1523 /*******************************************************************************
1524 * Register : WAKE_UP_DUR
1525 * Address : 0X5C
1526 * Bit Group Name: SLEEP_DUR
1527 * Permission : RW
1528 *******************************************************************************/
1529 #define LSM6DS3_IMU_SLEEP_DUR_MASK 0x0F
1530 #define LSM6DS3_IMU_SLEEP_DUR_POSITION 0
1531 
1532 /*******************************************************************************
1533 * Register : WAKE_UP_DUR
1534 * Address : 0X5C
1535 * Bit Group Name: TIMER_HR
1536 * Permission : RW
1537 *******************************************************************************/
1538 typedef enum {
1539  LSM6DS3_IMU_TIMER_HR_6_4ms = 0x00,
1540  LSM6DS3_IMU_TIMER_HR_25us = 0x10,
1541 } LSM6DS3_IMU_TIMER_HR_t;
1542 
1543 /*******************************************************************************
1544 * Register : WAKE_UP_DUR
1545 * Address : 0X5C
1546 * Bit Group Name: WAKE_DUR
1547 * Permission : RW
1548 *******************************************************************************/
1549 #define LSM6DS3_IMU_WAKE_DUR_MASK 0x60
1550 #define LSM6DS3_IMU_WAKE_DUR_POSITION 5
1551 
1552 /*******************************************************************************
1553 * Register : FREE_FALL
1554 * Address : 0X5D
1555 * Bit Group Name: FF_DUR
1556 * Permission : RW
1557 *******************************************************************************/
1558 #define LSM6DS3_IMU_FF_FREE_FALL_DUR_MASK 0xF8
1559 #define LSM6DS3_IMU_FF_FREE_FALL_DUR_POSITION 3
1560 #define LSM6DS3_IMU_FF_WAKE_UP_DUR_MASK 0x80
1561 #define LSM6DS3_IMU_FF_WAKE_UP_DUR_POSITION 7
1562 
1563 
1564 /*******************************************************************************
1565 * Register : FREE_FALL
1566 * Address : 0X5D
1567 * Bit Group Name: FF_THS
1568 * Permission : RW
1569 *******************************************************************************/
1570 typedef enum {
1571  LSM6DS3_IMU_FF_THS_5 = 0x00,
1572  LSM6DS3_IMU_FF_THS_7 = 0x01,
1573  LSM6DS3_IMU_FF_THS_8 = 0x02,
1574  LSM6DS3_IMU_FF_THS_10 = 0x03,
1575  LSM6DS3_IMU_FF_THS_11 = 0x04,
1576  LSM6DS3_IMU_FF_THS_13 = 0x05,
1577  LSM6DS3_IMU_FF_THS_15 = 0x06,
1578  LSM6DS3_IMU_FF_THS_16 = 0x07,
1579 } LSM6DS3_IMU_FF_THS_t;
1580 
1581 /*******************************************************************************
1582 * Register : MD1_CFG
1583 * Address : 0X5E
1584 * Bit Group Name: INT1_TIMER
1585 * Permission : RW
1586 *******************************************************************************/
1587 typedef enum {
1588  LSM6DS3_IMU_INT1_TIMER_DISABLED = 0x00,
1589  LSM6DS3_IMU_INT1_TIMER_ENABLED = 0x01,
1590 } LSM6DS3_IMU_INT1_TIMER_t;
1591 
1592 /*******************************************************************************
1593 * Register : MD1_CFG
1594 * Address : 0X5E
1595 * Bit Group Name: INT1_TILT
1596 * Permission : RW
1597 *******************************************************************************/
1598 typedef enum {
1599  LSM6DS3_IMU_INT1_TILT_DISABLED = 0x00,
1600  LSM6DS3_IMU_INT1_TILT_ENABLED = 0x02,
1601 } LSM6DS3_IMU_INT1_TILT_t;
1602 
1603 /*******************************************************************************
1604 * Register : MD1_CFG
1605 * Address : 0X5E
1606 * Bit Group Name: INT1_6D
1607 * Permission : RW
1608 *******************************************************************************/
1609 typedef enum {
1610  LSM6DS3_IMU_INT1_6D_DISABLED = 0x00,
1611  LSM6DS3_IMU_INT1_6D_ENABLED = 0x04,
1612 } LSM6DS3_IMU_INT1_6D_t;
1613 
1614 /*******************************************************************************
1615 * Register : MD1_CFG
1616 * Address : 0X5E
1617 * Bit Group Name: INT1_TAP
1618 * Permission : RW
1619 *******************************************************************************/
1620 typedef enum {
1621  LSM6DS3_IMU_INT1_TAP_DISABLED = 0x00,
1622  LSM6DS3_IMU_INT1_TAP_ENABLED = 0x08,
1623 } LSM6DS3_IMU_INT1_TAP_t;
1624 
1625 /*******************************************************************************
1626 * Register : MD1_CFG
1627 * Address : 0X5E
1628 * Bit Group Name: INT1_FF
1629 * Permission : RW
1630 *******************************************************************************/
1631 typedef enum {
1632  LSM6DS3_IMU_INT1_FF_DISABLED = 0x00,
1633  LSM6DS3_IMU_INT1_FF_ENABLED = 0x10,
1634 } LSM6DS3_IMU_INT1_FF_t;
1635 
1636 /*******************************************************************************
1637 * Register : MD1_CFG
1638 * Address : 0X5E
1639 * Bit Group Name: INT1_WU
1640 * Permission : RW
1641 *******************************************************************************/
1642 typedef enum {
1643  LSM6DS3_IMU_INT1_WU_DISABLED = 0x00,
1644  LSM6DS3_IMU_INT1_WU_ENABLED = 0x20,
1645 } LSM6DS3_IMU_INT1_WU_t;
1646 
1647 /*******************************************************************************
1648 * Register : MD1_CFG
1649 * Address : 0X5E
1650 * Bit Group Name: INT1_SINGLE_TAP
1651 * Permission : RW
1652 *******************************************************************************/
1653 typedef enum {
1654  LSM6DS3_IMU_INT1_SINGLE_TAP_DISABLED = 0x00,
1655  LSM6DS3_IMU_INT1_SINGLE_TAP_ENABLED = 0x40,
1656 } LSM6DS3_IMU_INT1_SINGLE_TAP_t;
1657 
1658 /*******************************************************************************
1659 * Register : MD1_CFG
1660 * Address : 0X5E
1661 * Bit Group Name: INT1_SLEEP
1662 * Permission : RW
1663 *******************************************************************************/
1664 typedef enum {
1665  LSM6DS3_IMU_INT1_SLEEP_DISABLED = 0x00,
1666  LSM6DS3_IMU_INT1_SLEEP_ENABLED = 0x80,
1667 } LSM6DS3_IMU_INT1_SLEEP_t;
1668 
1669 /*******************************************************************************
1670 * Register : MD2_CFG
1671 * Address : 0X5F
1672 * Bit Group Name: INT2_TIMER
1673 * Permission : RW
1674 *******************************************************************************/
1675 typedef enum {
1676  LSM6DS3_IMU_INT2_TIMER_DISABLED = 0x00,
1677  LSM6DS3_IMU_INT2_TIMER_ENABLED = 0x01,
1678 } LSM6DS3_IMU_INT2_TIMER_t;
1679 
1680 /*******************************************************************************
1681 * Register : MD2_CFG
1682 * Address : 0X5F
1683 * Bit Group Name: INT2_TILT
1684 * Permission : RW
1685 *******************************************************************************/
1686 typedef enum {
1687  LSM6DS3_IMU_INT2_TILT_DISABLED = 0x00,
1688  LSM6DS3_IMU_INT2_TILT_ENABLED = 0x02,
1689 } LSM6DS3_IMU_INT2_TILT_t;
1690 
1691 /*******************************************************************************
1692 * Register : MD2_CFG
1693 * Address : 0X5F
1694 * Bit Group Name: INT2_6D
1695 * Permission : RW
1696 *******************************************************************************/
1697 typedef enum {
1698  LSM6DS3_IMU_INT2_6D_DISABLED = 0x00,
1699  LSM6DS3_IMU_INT2_6D_ENABLED = 0x04,
1700 } LSM6DS3_IMU_INT2_6D_t;
1701 
1702 /*******************************************************************************
1703 * Register : MD2_CFG
1704 * Address : 0X5F
1705 * Bit Group Name: INT2_TAP
1706 * Permission : RW
1707 *******************************************************************************/
1708 typedef enum {
1709  LSM6DS3_IMU_INT2_TAP_DISABLED = 0x00,
1710  LSM6DS3_IMU_INT2_TAP_ENABLED = 0x08,
1711 } LSM6DS3_IMU_INT2_TAP_t;
1712 
1713 /*******************************************************************************
1714 * Register : MD2_CFG
1715 * Address : 0X5F
1716 * Bit Group Name: INT2_FF
1717 * Permission : RW
1718 *******************************************************************************/
1719 typedef enum {
1720  LSM6DS3_IMU_INT2_FF_DISABLED = 0x00,
1721  LSM6DS3_IMU_INT2_FF_ENABLED = 0x10,
1722 } LSM6DS3_IMU_INT2_FF_t;
1723 
1724 /*******************************************************************************
1725 * Register : MD2_CFG
1726 * Address : 0X5F
1727 * Bit Group Name: INT2_WU
1728 * Permission : RW
1729 *******************************************************************************/
1730 typedef enum {
1731  LSM6DS3_IMU_INT2_WU_DISABLED = 0x00,
1732  LSM6DS3_IMU_INT2_WU_ENABLED = 0x20,
1733 } LSM6DS3_IMU_INT2_WU_t;
1734 
1735 /*******************************************************************************
1736 * Register : MD2_CFG
1737 * Address : 0X5F
1738 * Bit Group Name: INT2_SINGLE_TAP
1739 * Permission : RW
1740 *******************************************************************************/
1741 typedef enum {
1742  LSM6DS3_IMU_INT2_SINGLE_TAP_DISABLED = 0x00,
1743  LSM6DS3_IMU_INT2_SINGLE_TAP_ENABLED = 0x40,
1744 } LSM6DS3_IMU_INT2_SINGLE_TAP_t;
1745 
1746 /*******************************************************************************
1747 * Register : MD2_CFG
1748 * Address : 0X5F
1749 * Bit Group Name: INT2_SLEEP
1750 * Permission : RW
1751 *******************************************************************************/
1752 typedef enum {
1753  LSM6DS3_IMU_INT2_SLEEP_DISABLED = 0x00,
1754  LSM6DS3_IMU_INT2_SLEEP_ENABLED = 0x80,
1755 } LSM6DS3_IMU_INT2_SLEEP_t;
1756 
1757 
1758 struct IMU_settings {
1759  // Accelerometer settings
1760  uint8_t accel_enable;
1761  uint16_t accel_range;
1762  uint16_t accel_samplerate;
1763  uint16_t accel_bandwidth;
1764 
1765  uint8_t accel_FIFO_enable;
1766  uint8_t accel_FIFO_decimation;
1767 
1768  // Gyroscope settings
1769  uint8_t gyro_enable;
1770  uint16_t gyro_range;
1771  uint16_t gyro_samplerate;
1772  uint16_t gyro_bandwidth;
1773 
1774  uint8_t gyro_FIFO_enable;
1775  uint8_t gyro_FIFO_decimation;
1776 
1777  // Temperature settings
1778  uint8_t temp_enable;
1779 
1780  // FIFO control data
1781  uint16_t FIFO_threshold;
1782  uint16_t FIFO_samplerate;
1783  uint8_t FIFO_mode;
1784 };
1785 
1789 void LSM6DS3_init(void);
1790 
1794 void LSM6DS3_who_am_i(void);
1795 
1809 void LSM6DS3_config();
1810 
1816 void LSM6DS3_set_accel_power_down_mode();
1817 
1823 void LSM6DS3_set_accel_low_power_mode(uint16_t value);
1824 
1830 void LSM6DS3_set_accel_normal_mode(uint16_t value);
1831 
1837 void LSM6DS3_set_accel_high_performance_mode(uint16_t value);
1838 
1842 void LSM6DS3_read_accl_data(int16_t *x_axis, int16_t *y_axis, int16_t *z_axis);
1843 
1844 
1851 int16_t LSM6DS3_accelData_in_g(int16_t raw_data);
1852 
1856 void LSM6DS3_set_gyro_active_mode();
1857 
1861 void LSM6DS3_set_gyro_sleep_mode();
1862 
1866 void LSM6DS3_read_gyro_data(int16_t *gyro_x, int16_t *gyro_y, int16_t *gyro_z);
1867 
1874 float LSM6DS3_gyroData_in_dps(int16_t raw_data);
1875 
1879 void LSM6DS3_FIFO_config(void);
1880 
1884 void LSM6DS3_clear_FIFO_buffer(void);
1885 
1889 uint16_t LSM6DS3_read_FIFO_status(void);
1890 
1894 int16_t LSM6DS3_read_FIFO_buffer(void);
1895 
1899 void LSM6DS3_tap_detect_config();
1900 
1901 #endif /* LSM6DS3_H */
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